From a186a9a6be2cb0ece7ecf0bcc27e813f5534603d Mon Sep 17 00:00:00 2001
From: "github-classroom[bot]"
 <66690702+github-classroom[bot]@users.noreply.github.com>
Date: Wed, 10 Sep 2025 21:59:56 +0000
Subject: Initial commit

---
 task1/.gitignore     | 18 ++++++++++++++++++
 task1/card7seg.sv    |  6 ++++++
 task1/tb_card7seg.sv |  8 ++++++++
 3 files changed, 32 insertions(+)
 create mode 100644 task1/.gitignore
 create mode 100644 task1/card7seg.sv
 create mode 100644 task1/tb_card7seg.sv

(limited to 'task1')

diff --git a/task1/.gitignore b/task1/.gitignore
new file mode 100644
index 0000000..b0345dc
--- /dev/null
+++ b/task1/.gitignore
@@ -0,0 +1,18 @@
+.DS_Store
+transcript
+tcl_stacktrace.txt
+c5_pin_model_dump.txt
+*.mti
+*.mpf
+*.wlf
+*.qdb
+*.qpg
+*.qtl
+*.qpf
+*.sof
+*.bak
+work/
+db/
+incremental_db/
+simulation/
+output_files/
diff --git a/task1/card7seg.sv b/task1/card7seg.sv
new file mode 100644
index 0000000..b994e3e
--- /dev/null
+++ b/task1/card7seg.sv
@@ -0,0 +1,6 @@
+module card7seg(input logic [3:0] SW, output logic [6:0] HEX0);
+		
+   // your code goes here
+	
+endmodule
+
diff --git a/task1/tb_card7seg.sv b/task1/tb_card7seg.sv
new file mode 100644
index 0000000..3a985c9
--- /dev/null
+++ b/task1/tb_card7seg.sv
@@ -0,0 +1,8 @@
+module tb_card7seg();
+
+// Your testbench goes here. Make sure your tests exercise the entire design
+// in the .sv file.  Note that in our tests the simulator will exit after
+// 10,000 ticks (equivalent to "initial #10000 $finish();").
+						
+endmodule
+
-- 
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