From a186a9a6be2cb0ece7ecf0bcc27e813f5534603d Mon Sep 17 00:00:00 2001
From: "github-classroom[bot]"
 <66690702+github-classroom[bot]@users.noreply.github.com>
Date: Wed, 10 Sep 2025 21:59:56 +0000
Subject: Initial commit

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 task4/datapath.sv | 17 +++++++++++++++++
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+module datapath(input logic slow_clock, input logic fast_clock, input logic resetb,
+                input logic load_pcard1, input logic load_pcard2, input logic load_pcard3,
+                input logic load_dcard1, input logic load_dcard2, input logic load_dcard3,
+                output logic [3:0] pcard3_out,
+                output logic [3:0] pscore_out, output logic [3:0] dscore_out,
+                output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3,
+                output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0);
+
+// The code describing your datapath will go here.  Your datapath 
+// will hierarchically instantiate six card7seg blocks, two scorehand
+// blocks, and a dealcard block.  The registers may either be instatiated
+// or included as sequential always blocks directly in this file.
+//
+// Follow the block diagram in the Lab 1 handout closely as you write this code.
+
+endmodule
+
-- 
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