From a186a9a6be2cb0ece7ecf0bcc27e813f5534603d Mon Sep 17 00:00:00 2001
From: "github-classroom[bot]"
 <66690702+github-classroom[bot]@users.noreply.github.com>
Date: Wed, 10 Sep 2025 21:59:56 +0000
Subject: Initial commit

---
 task4/scorehand.sv | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 task4/scorehand.sv

(limited to 'task4/scorehand.sv')

diff --git a/task4/scorehand.sv b/task4/scorehand.sv
new file mode 100644
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+++ b/task4/scorehand.sv
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+module scorehand(input logic [3:0] card1, input logic [3:0] card2, input logic [3:0] card3, output logic [3:0] total);
+
+// The code describing scorehand will go here.  Remember this is a combinational
+// block. The function is described in the handout. Be sure to review Verilog
+// notes on bitwidth mismatches and signed/unsigned numbers.
+
+endmodule
+
-- 
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