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9 files changed, 75 insertions, 0 deletions

diff --git a/task4/.gitignore b/task4/.gitignore
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+.DS_Store
+transcript
+tcl_stacktrace.txt
+c5_pin_model_dump.txt
+*.mti
+*.mpf
+*.wlf
+*.qdb
+*.qpg
+*.qtl
+*.qpf
+*.sof
+*.bak
+work/
+db/
+incremental_db/
+simulation/
+output_files/
diff --git a/task4/README.md b/task4/README.md
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+# Contributions
+List of contributions made by members of the team.
+
+## Contributions made by ABC DEF
+- contribution 1
+- contribution 2
+
+## Contributions made by TUV XYZ
+- contribution 1
+- contribution 2
+
+
diff --git a/task4/reuleaux.sv b/task4/reuleaux.sv
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+++ b/task4/reuleaux.sv
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+module reuleaux(input logic clk, input logic rst_n, input logic [2:0] colour,
+                input logic [7:0] centre_x, input logic [6:0] centre_y, input logic [7:0] diameter,
+                input logic start, output logic done,
+                output logic [7:0] vga_x, output logic [6:0] vga_y,
+                output logic [2:0] vga_colour, output logic vga_plot);
+     // draw the Reuleaux triangle
+endmodule
+
diff --git a/task4/task4.sv b/task4/task4.sv
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+++ b/task4/task4.sv
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+module task4(input logic CLOCK_50, input logic [3:0] KEY,
+             input logic [9:0] SW, output logic [9:0] LEDR,
+             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
+             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
+             output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B,
+             output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK,
+             output logic [7:0] VGA_X, output logic [6:0] VGA_Y,
+             output logic [2:0] VGA_COLOUR, output logic VGA_PLOT);
+
+    // instantiate and connect the VGA adapter and your module
+
+endmodule: task4
diff --git a/task4/tb_rtl_reuleaux.sv b/task4/tb_rtl_reuleaux.sv
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+++ b/task4/tb_rtl_reuleaux.sv
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+module tb_rtl_reuleaux();
+
+// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks.
+
+endmodule: tb_rtl_reuleaux
diff --git a/task4/tb_rtl_task4.sv b/task4/tb_rtl_task4.sv
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index 0000000..47f6810
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+++ b/task4/tb_rtl_task4.sv
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+module tb_rtl_task4();
+
+// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks.
+
+endmodule: tb_rtl_task4
diff --git a/task4/tb_syn_reuleaux.sv b/task4/tb_syn_reuleaux.sv
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+++ b/task4/tb_syn_reuleaux.sv
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+module tb_syn_reuleaux();
+
+// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks.
+
+endmodule: tb_syn_reuleaux
diff --git a/task4/tb_syn_task4.sv b/task4/tb_syn_task4.sv
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index 0000000..8c66b3f
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+++ b/task4/tb_syn_task4.sv
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+module tb_syn_task4();
+
+// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks.
+
+endmodule: tb_syn_task4
diff --git a/task4/tb_task4.sv b/task4/tb_task4.sv
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+++ b/task4/tb_task4.sv
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+module tb_task4();
+
+// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks.
+
+endmodule: tb_task4