1 files changed, 34 insertions, 9 deletions
diff --git a/task4/task4.sv b/task4/task4.sv
index 71d43be..1426a72 100644
--- a/task4/task4.sv
+++ b/task4/task4.sv
@@ -1,12 +1,37 @@
-module task4(input logic CLOCK_50, input logic [3:0] KEY,
-             input logic [9:0] SW, output logic [9:0] LEDR,
-             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
-             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
-             output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B,
-             output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK,
-             output logic [7:0] VGA_X, output logic [6:0] VGA_Y,
-             output logic [2:0] VGA_COLOUR, output logic VGA_PLOT);
+module task4(CLOCK_50, KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
+	VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_CLK, VGA_X, VGA_Y,
+	VGA_COLOUR, VGA_PLOT);
 
-    // instantiate and connect the VGA adapter and your module
+	input logic CLOCK_50;
+	input logic [3:0] KEY;
+	input logic [9:0] SW;
+	output logic VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT;
+	output logic [2:0] VGA_COLOUR;
+	output logic [6:0] VGA_Y, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
+	output logic [7:0] VGA_X, VGA_R, VGA_G, VGA_B;
+	output logic [9:0] LEDR;
+
+	logic resetn, start, done;
+	logic [2:0] colour;
+	logic [6:0] center_y;
+	logic [7:0] center_x, diameter;
+
+	assign resetn = KEY[3];
+	assign start = ~KEY[0];
+	assign colour = 3'b010;
+	assign LEDR[0] = done;
+
+	assign center_x = 8'd80;
+	assign center_y = 7'd60;
+	assign diameter = SW[7:0];
+
+	vga_adapter #(.RESOLUTION("160x120")) U0(resetn, CLOCK_50,
+		VGA_COLOUR, VGA_X, VGA_Y, VGA_PLOT,
+		{VGA_R, 2'b00}, {VGA_G, 2'b00}, {VGA_B, 2'b00},
+		VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK);
+
+	reuleaux U1(CLOCK_50, resetn, colour, center_x, center_y, diameter,
+		start, done, VGA_X, VGA_Y, VGA_COLOUR, VGA_PLOT);
 
 endmodule: task4
+