From 21bf9f58b3c3b90cdff6541f42fe2dce21d68032 Mon Sep 17 00:00:00 2001 From: Warrick Lo Date: Sun, 1 Mar 2026 07:20:20 -0800 Subject: Add task 2 code Signed-off-by: Warrick Lo --- task2/fillscreen.sv | 56 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 6 deletions(-) (limited to 'task2/fillscreen.sv') diff --git a/task2/fillscreen.sv b/task2/fillscreen.sv index 323e7a5..de7a928 100644 --- a/task2/fillscreen.sv +++ b/task2/fillscreen.sv @@ -1,7 +1,51 @@ -module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour, - input logic start, output logic done, - output logic [7:0] vga_x, output logic [6:0] vga_y, - output logic [2:0] vga_colour, output logic vga_plot); - // fill the screen -endmodule +module fillscreen(clk, rst_n, colour, start, + done, vga_x, vga_y, vga_colour, vga_plot); + input logic clk, rst_n, start; + input logic [2:0] colour; + output logic done, vga_plot; + output logic [2:0] vga_colour; + output logic [6:0] vga_y; + output logic [7:0] vga_x; + + logic clear; + logic [6:0] y_next; + logic [7:0] x_next; + + assign vga_colour = clear ? 3'b000 : vga_x[2:0]; + assign vga_plot = clear || (start && ~done); + assign x_next = vga_x + 1; + assign y_next = vga_y + 1; + + always_ff @(posedge clk) begin + if (~rst_n) begin + done <= 1'b0; + vga_x <= 8'b0; + vga_y <= 7'b0; + /* Start clearing the screen. */ + clear <= 1'b1; + end + + if (clear || (start && ~done)) begin + if (vga_y < 120) begin + /* Check for one column less since it takes + * one clock cycle to reset and increment. */ + if (vga_x < 159) + vga_x <= x_next; + else begin + vga_x <= 8'b0; + vga_y <= y_next; + end + end else begin + if (clear) + clear <= 1'b0; + else + done <= 1'b1; + vga_x <= 8'b0; + vga_y <= 7'b0; + end + end else if (~start && done) + done <= 1'b0; + end + +endmodule: fillscreen -- cgit v1.2.3