From e16feba0f56963d22c6f7820815f0b651c78bbe5 Mon Sep 17 00:00:00 2001
From: Warrick Lo <wlo@warricklo.net>
Date: Wed, 4 Mar 2026 14:53:56 -0800
Subject: Move fillscreen to a separate module

Signed-off-by: Warrick Lo <wlo@warricklo.net>
---
 task4/reuleaux.sv | 36 ++++++------------------------------
 1 file changed, 6 insertions(+), 30 deletions(-)

(limited to 'task4/reuleaux.sv')

diff --git a/task4/reuleaux.sv b/task4/reuleaux.sv
index cc89f4f..e518b63 100644
--- a/task4/reuleaux.sv
+++ b/task4/reuleaux.sv
@@ -14,7 +14,7 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
 	output logic [6:0] vga_y;
 	output logic [7:0] vga_x;
 
-	logic clear, ready, vga_plot_next;
+	logic clear, vga_plot_next;
 	logic [2:0] octant;
 	/* Auxiliary value for calculations. 21-bit number since we multiply
 	 * 8-bit and 13-bit numbers together. */
@@ -114,42 +114,19 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
 	always_ff @(posedge clk) begin
 		if (~rst_n) begin
 			done <= 1'b0;
-			ready <= 1'b0;
 
-			/* Start clearing the screen. */
-			clear <= 1'b1;
+			/* Initialise the registers for the circle algorithm. */
 			vga_x <= 8'b0;
 			vga_y <= 7'b0;
-			vga_plot <= 1'b1;
-		end
-
-		/* Clear the screen. */
-		if (clear) begin
-			if (vga_y < 120) begin
-				/* Check for one column less since it takes
-				 * one clock cycle to reset and increment. */
-				if (vga_x < 159)
-					vga_x <= vga_x + 1;
-				else begin
-					vga_x <= 8'b0;
-					vga_y <= vga_y + 1;
-				end
-			end else begin
-				clear <= 1'b0;
-				ready <= 1'b1;
-				vga_x <= 8'b0;
-				vga_y <= 7'b0;
-				vga_plot <= 1'b0;
-			end
-		/* Initialise the registers for the circle algorithm. */
-		end else if (ready && start && ~done) begin
-			ready <= 1'b0;
+			vga_plot <= 1'b0;
 			octant <= 3'b0;
 			offset_y <= 9'b0;
 			offset_x <= radius;
 			crit <= 1 - radius;
+		end
+
 		/* Draw the circle using the Bresenham circle algorithm. */
-		end else if (start && ~done) begin
+		if (start && ~done) begin
 			if (offset_y <= offset_x) begin
 				if ((vga_x_next >= 0) && (vga_x_next <= `VGA_W))
 					vga_x <= vga_x_next;
@@ -174,7 +151,6 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
 			/* Finished. */
 			end else begin
 				done <= 1'b1;
-				ready <= 1'b1;
 				vga_plot <= 1'b0;
 			end
 		/* Wait for start to be deasserted. */
-- 
cgit v1.2.3