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| author | Warrick Lo <wlo@warricklo.net> | 2026-05-23 22:10:42 -0700 |
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| committer | Warrick Lo <wlo@warricklo.net> | 2026-05-23 22:10:42 -0700 |
| commit | 2090c730e8a3ba069da7459b3130bf351403d6ae (patch) | |
| tree | c67d065b77883b3d542479b97cef2ea554bbea02 | |
| parent | Merge branch 'chat/simple-alu-formal-verif' (diff) | |
| download | montreal-2090c730e8a3ba069da7459b3130bf351403d6ae.tar.xz montreal-2090c730e8a3ba069da7459b3130bf351403d6ae.zip | |
Add WaveDrom diagrams for instructions to README
Signed-off-by: Warrick Lo <wlo@warricklo.net>
| -rw-r--r-- | README.md | 50 |
1 files changed, 28 insertions, 22 deletions
@@ -1,8 +1,10 @@ -# Montreal +Montreal +======== A RISC-V RV32E processor designed for TinyTapeout. -## [RV32E](https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html) +[RV32E](https://docs.riscv.org/reference/isa/unpriv/unpriv-index.html) +---------------------------------------------------------------------- Reduces number of integer registers to 16 general-purpose registers (x0-x15). Upper 16 registers consume around one quarter of the total area of the core excluding memories, thus their removal saves around 25% core area with a corresponding core power reduction. @@ -28,26 +30,32 @@ Each register is 32 bits wide. | x15 | sixth function argument | | | pc | program counter | Address of current instruction | -## INSTRUCTION SET +INSTRUCTION SET +--------------- + ### Formats -``` - 31 25 24 20 19 15 14 12 11 7 6 0 - +----------+--------+--------+-------+--------+----------+ -R | funct7 | rs2 | rs1 | funct3| rd | opcode | - +----------+--------+--------+-------+--------+----------+ - (src2) (src1) (dest) - +-------------------+--------+-------+--------+----------+ -I | imm[11:0] | rs1 | funct3| rd | opcode | - +-------------------+--------+-------+--------+----------+ - (src) (dest) - +----------+--------+--------+-------+--------+----------+ -I-sh | imm[11:5]|imm[4:0]| rs1 | funct3| rd | opcode | - +----------+--------+--------+-------+--------+----------+ - (src) (dest) -``` - -I-sh is the shift variant of I-type: `imm[11:5]` acts as a discriminator (like `funct7`), and `imm[4:0]` is the shift amount (shamt). + + + + + + + + + + + + + + + + + + + + + ### R-Type (Register-to-register) @@ -83,5 +91,3 @@ I-sh is the shift variant of I-type: `imm[11:5]` acts as a discriminator (like ` | SLLI | Shift rs1 left by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `001` \| `0010011` | | SRLI | Shift rs1 right by shamt (`imm[4:0]`), logical, store in rd. | `0000000` \| `101` \| `0010011` | | SRAI | Shift rs1 right by shamt (`imm[4:0]`), arithmetic, store in rd. | `0100000` \| `101` \| `0010011` | - - |