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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:44:02 +0000 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-17 00:44:02 +0000 |
| commit | ef9254b3303a03ea4ab3c32aaf1d79df651e3b92 (patch) | |
| tree | dea7bd703dca6221b577b5d5f87b1f985f9f3297 /rtl/config_pkg.sv | |
| parent | regfile: refactor: 'chunks' are now 'slices' (diff) | |
| download | montreal-ef9254b3303a03ea4ab3c32aaf1d79df651e3b92.tar.xz montreal-ef9254b3303a03ea4ab3c32aaf1d79df651e3b92.zip | |
Move design parameters to config_pkg
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to '')
| -rw-r--r-- | rtl/config_pkg.sv | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/rtl/config_pkg.sv b/rtl/config_pkg.sv new file mode 100644 index 0000000..0120b14 --- /dev/null +++ b/rtl/config_pkg.sv @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ + +package config_pkg; + + /* Word width as defined in the RISC-V spec. */ + localparam int unsigned XLEN = 32; + + /* We use a byte-sliced datapath, inspired by the + * classic bit-sliced architecture of old CPUs. */ + localparam int unsigned SLICE_WIDTH = 8; + + /* The RV32E ISA defines 16 general-purpose registers. + * We have two read ports to allow for pipelined reads. */ + localparam int unsigned REG_ADDR_WIDTH = 4; + localparam int unsigned REG_NUM_READ_PORTS = 2; + +endpackage : config_pkg |