3 files changed, 37 insertions, 10 deletions
diff --git a/rtl/config_pkg.sv b/rtl/config_pkg.sv
new file mode 100644
index 0000000..0120b14
--- /dev/null
+++ b/rtl/config_pkg.sv
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: CERN-OHL-P-2.0 */
+
+package config_pkg;
+
+  /* Word width as defined in the RISC-V spec. */
+  localparam int unsigned XLEN = 32;
+
+  /* We use a byte-sliced datapath, inspired by the
+   * classic bit-sliced architecture of old CPUs. */
+  localparam int unsigned SLICE_WIDTH      = 8;
+
+  /* The RV32E ISA defines 16 general-purpose registers.
+   * We have two read ports to allow for pipelined reads. */
+  localparam int unsigned REG_ADDR_WIDTH     = 4;
+  localparam int unsigned REG_NUM_READ_PORTS = 2;
+
+endpackage : config_pkg
diff --git a/rtl/montreal_pkg.sv b/rtl/montreal_pkg.sv
new file mode 100644
index 0000000..b3a13a0
--- /dev/null
+++ b/rtl/montreal_pkg.sv
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: CERN-OHL-P-2.0 */
+
+package montreal_pkg;
+
+  typedef logic unsigned [config_pkg::XLEN-1:0]        word_t;
+  typedef logic unsigned [config_pkg::SLICE_WIDTH-1:0] slice_t;
+
+endpackage : montreal_pkg
diff --git a/rtl/regfile.sv b/rtl/regfile.sv
index 8ca992c..e18301a 100644
--- a/rtl/regfile.sv
+++ b/rtl/regfile.sv
@@ -15,18 +15,20 @@
  * read ports (default 2). Register 0 is fixed to 0 for all reads.
  */
 
-module regfile #(
-  parameter int unsigned WORD_WIDTH     = 32,
-  parameter int unsigned ADDR_WIDTH     = 4,
-  parameter int unsigned SLICE_WIDTH    = 8,
-  parameter int unsigned NUM_READ_PORTS = 2,
-
-  localparam int unsigned NUM_WORDS  = 2 ** ADDR_WIDTH,
-  localparam int unsigned NUM_SLICES = WORD_WIDTH / SLICE_WIDTH
+module regfile
+  import montreal_pkg::*;
+#(
+  parameter int unsigned XLEN           = config_pkg::XLEN,
+  parameter int unsigned SLICE_WIDTH    = config_pkg::SLICE_WIDTH,
+  parameter int unsigned ADDR_WIDTH     = config_pkg::REG_ADDR_WIDTH,
+  parameter int unsigned NUM_READ_PORTS = config_pkg::REG_NUM_READ_PORTS,
+
+  localparam int unsigned NUM_WORDS        = 2 ** ADDR_WIDTH,
+  localparam int unsigned SLICE_ADDR_WIDTH = $clog2(XLEN / SLICE_WIDTH)
 ) (
   input logic clk_i,
   input logic rst_ni,
-  input logic [$clog2(NUM_SLICES)-1:0] slice_sel_i,
+  input logic [SLICE_ADDR_WIDTH-1:0] slice_sel_i,
 
   input  logic [NUM_READ_PORTS-1:0][ADDR_WIDTH-1:0]  raddr_i,
   output logic [NUM_READ_PORTS-1:0][SLICE_WIDTH-1:0] rdata_o,
@@ -36,7 +38,7 @@ module regfile #(
   input logic [SLICE_WIDTH-1:0] wdata_i
 );
 
-  logic [NUM_WORDS-1:0][WORD_WIDTH-1:0] register;
+  logic [NUM_WORDS-1:0][XLEN-1:0] register;
 
   always_comb begin
     for (int i = 0; i < NUM_READ_PORTS; i++) begin : gen_read_block