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-rw-r--r--dv/formal/simple_alu/simple_alu_bind.sv15
1 files changed, 15 insertions, 0 deletions
diff --git a/dv/formal/simple_alu/simple_alu_bind.sv b/dv/formal/simple_alu/simple_alu_bind.sv
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+++ b/dv/formal/simple_alu/simple_alu_bind.sv
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+// Bind file for simple_alu formal verification.
+// Attaches simple_alu_fv to every instance of simple_alu in the design.
+// RTL is completely unaware of this file.
+//
+// bind <dut_module> <fv_module> <instance_name> (<port_connections>);
+
+bind simple_alu simple_alu_fv u_simple_alu_fv (
+ .clk (clk),
+ .rst (rst),
+ .a (a),
+ .b (b),
+ .sel (sel),
+ .y (y),
+ .overflow (overflow)
+);