Add testbenches

Signed-off-by: Warrick Lo <wlo@warricklo.net>

5 files changed, 103 insertions, 0 deletions

diff --git a/schematic/mosfet-check.tcl b/schematic/mosfet-check.tcl
new file mode 100644
index 0000000..3cdfc23
--- /dev/null
+++ b/schematic/mosfet-check.tcl
@@ -0,0 +1,27 @@
+xschem annotate_op
+xschem unhilight_all
+
+foreach {i n t} [xschem instance_list] {
+	if {$t eq {nmos} || $t eq {pmos}} {
+		set inst x[string tolower $i]
+		lassign [array get ::ngspice::ngspice_data *$inst.*\\\[vth\\\]*] node_vth vth
+		lassign [array get ::ngspice::ngspice_data *$inst.*\\\[vgs\\\]*] node_vgs vgs
+		lassign [array get ::ngspice::ngspice_data *$inst.*\\\[vds\\\]*] node_vds vds
+		set vov [expr {$vgs - $vth}]
+
+		if {$vov <= 0} {
+			# Off.
+			xschem set hilight_color 0
+		} elseif {$vds < $vov} {
+			# Linear/triode.
+			xschem set hilight_color 1
+		} else {
+			# Saturation.
+			xschem set hilight_color 2
+		}
+
+		xschem hilight_instname $i fast
+	}
+}
+
+xschem redraw
diff --git a/schematic/opamp_tb_cl.sch b/schematic/opamp_tb_cl.sch
new file mode 100644
index 0000000..d8fa9cd
--- /dev/null
+++ b/schematic/opamp_tb_cl.sch
@@ -0,0 +1,18 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+C {opamp.sym} 60 50 0 0 {name=x1}
+C {lab_wire.sym} 60 0 0 0 {name=p1 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 60 100 2 1 {name=p2 sig_type=std_logic lab=0}
+C {lab_wire.sym} 0 30 0 0 {name=p3 sig_type=std_logic lab=IP}
+C {lab_wire.sym} 0 70 0 0 {name=p4 sig_type=std_logic lab=OUT}
+C {lab_wire.sym} 120 50 0 1 {name=p5 sig_type=std_logic lab=OUT}
+C {code_shown.sym} 180 0 0 0 {name=SPICE only_toplevel=false value=".LIB /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.AC DEC 1k 100m 1G
+
+VDD VDD 0 DC 1.8
+VIP IP 0 DC 900m AC 100u"}
diff --git a/schematic/opamp_tb_ol.sch b/schematic/opamp_tb_ol.sch
new file mode 100644
index 0000000..29f977e
--- /dev/null
+++ b/schematic/opamp_tb_ol.sch
@@ -0,0 +1,20 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+C {opamp.sym} 60 50 0 0 {name=x1}
+C {lab_wire.sym} 60 0 0 0 {name=p1 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 60 100 2 1 {name=p2 sig_type=std_logic lab=0}
+C {lab_wire.sym} 0 30 0 0 {name=p3 sig_type=std_logic lab=IP}
+C {lab_wire.sym} 0 70 0 0 {name=p4 sig_type=std_logic lab=IN}
+C {lab_wire.sym} 120 50 0 1 {name=p5 sig_type=std_logic lab=OUT}
+C {code_shown.sym} 180 0 0 0 {name=SPICE only_toplevel=false value=".LIB /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.AC DEC 1k 100m 1G
+
+VDD VDD 0 DC 1.8
+VICM VICM 0 DC 900m
+VIP IP VICM DC 0 AC 50u 0
+VIN IN VICM DC 0 AC 50u 180"}
diff --git a/schematic/opamp_tb_op.sch b/schematic/opamp_tb_op.sch
new file mode 100644
index 0000000..eca2f21
--- /dev/null
+++ b/schematic/opamp_tb_op.sch
@@ -0,0 +1,25 @@
+v {xschem version=3.4.8RC file_version=1.3}
+G {}
+K {}
+V {}
+S {}
+F {}
+E {}
+C {opamp.sym} 60 50 0 0 {name=x1}
+C {lab_wire.sym} 60 0 0 0 {name=p1 sig_type=std_logic lab=VDD}
+C {lab_wire.sym} 60 100 2 1 {name=p2 sig_type=std_logic lab=0}
+C {lab_wire.sym} 0 30 0 0 {name=p3 sig_type=std_logic lab=IN}
+C {lab_wire.sym} 0 70 0 0 {name=p4 sig_type=std_logic lab=IN}
+C {lab_wire.sym} 120 50 0 1 {name=p5 sig_type=std_logic lab=OUT}
+C {code_shown.sym} 180 0 0 0 {name=SPICE only_toplevel=false value=".LIB /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+.INCLUDE save_mos_params.spice
+.SAVE ALL
+
+.CONTROL
+OP
+WRITE opamp_tb_op.raw
+.ENDC
+
+VDD VDD 0 DC 1.8
+VIN IN 0 DC 0.9"}
diff --git a/schematic/simulation/save_mos_params.spice b/schematic/simulation/save_mos_params.spice
new file mode 100644
index 0000000..a6959aa
--- /dev/null
+++ b/schematic/simulation/save_mos_params.spice
@@ -0,0 +1,13 @@
+.CONTROL
+
+FOREACH param id gm vth vds
+	FOREACH pfet 1 2 3 8 9 10 11 12
+		SAVE @m.x1.xm{$pfet}.msky130_fd_pr__pfet_01v8_lvt[{$param}]
+	END
+
+	FOREACH nfet 4 5 6 7 13 14
+		SAVE @m.x1.xm{$nfet}.msky130_fd_pr__nfet_01v8_lvt[{$param}]
+	END
+END
+
+.ENDC