Add muli-core ARC4 cracking

Signed-off-by: Warrick Lo <wlo@warricklo.net>

19 files changed, 2416 insertions, 0 deletions

diff --git a/src/arc4.sv b/src/arc4.sv
new file mode 100644
index 0000000..453c1f2
--- /dev/null
+++ b/src/arc4.sv
@@ -0,0 +1,154 @@
+module arc4 (
+	input logic clk,
+	input logic rst_n,
+	input logic en,
+	output logic rdy,
+	input logic [23:0] key,
+
+	output logic [7:0] ct_addr,
+	input logic [7:0] ct_rddata,
+
+	output logic [7:0] pt_addr,
+	input logic [7:0] pt_rddata,
+	output logic [7:0] pt_wrdata,
+	output logic pt_wren
+);
+
+	logic s_wren;
+	logic [7:0] s_addr;
+	logic [7:0] s_wrdata, s_rddata;
+
+	logic i_en, i_rdy, i_wren;
+	logic [7:0] i_addr;
+	logic [7:0] i_wrdata;
+
+	logic k_en, k_rdy, k_wren;
+	logic [7:0] k_addr;
+	logic [7:0] k_wrdata;
+
+	logic p_en, p_rdy, p_s_wren, p_pt_wren;
+	logic [7:0] p_s_addr, p_ct_addr, p_pt_addr;
+	logic [7:0] p_s_wrdata, p_pt_wrdata;
+
+	enum logic [2:0] {
+		IDLE,
+		INIT_BEGIN,
+		INIT,
+		KSA_BEGIN,
+		KSA,
+		PRGA_BEGIN,
+		PRGA,
+		DONE
+	} state;
+
+	s_core_mem s (
+		.address(s_addr),
+		.clock(clk),
+		.data(s_wrdata),
+		.wren(s_wren),
+		.q(s_rddata)
+	);
+
+	init i (
+		.clk,
+		.rst_n,
+		.en(i_en),
+		.rdy(i_rdy),
+		.addr(i_addr),
+		.wrdata(i_wrdata),
+		.wren(i_wren)
+	);
+
+	ksa k (
+		.clk,
+		.rst_n,
+		.en(k_en),
+		.rdy(k_rdy),
+		.key,
+		.addr(k_addr),
+		.rddata(s_rddata),
+		.wrdata(k_wrdata),
+		.wren(k_wren)
+	);
+
+	prga p (
+		.clk,
+		.rst_n,
+		.en(p_en),
+		.rdy(p_rdy),
+		.key,
+		.s_addr(p_s_addr),
+		.s_rddata,
+		.s_wrdata(p_s_wrdata),
+		.s_wren(p_s_wren),
+		.ct_addr(p_ct_addr),
+		.ct_rddata,
+		.pt_addr(p_pt_addr),
+		.pt_rddata,
+		.pt_wrdata(p_pt_wrdata),
+		.pt_wren(p_pt_wren)
+	);
+
+	always_ff @(posedge clk) begin: fsm
+		if (~rst_n) begin
+			state <= IDLE;
+		end else unique case (state)
+			IDLE: if (en) state <= INIT_BEGIN;
+			INIT_BEGIN: if (i_rdy) state <= INIT;
+			INIT: if (i_rdy) state <= KSA_BEGIN;
+			KSA_BEGIN: if (k_rdy) state <= KSA;
+			KSA: if (k_rdy) state <= PRGA_BEGIN;
+			PRGA_BEGIN: if (p_rdy) state <= PRGA;
+			PRGA: if (p_rdy) state <= DONE;
+			DONE: state <= DONE;
+			default: state <= IDLE;
+		endcase
+	end: fsm
+
+	always_comb begin: controller
+		rdy = '0;
+
+		i_en = '0;
+		k_en = '0;
+		p_en = '0;
+
+		s_wren = '0;
+		s_addr = '0;
+		s_wrdata = '0;
+
+		ct_addr = '0;
+
+		pt_wren = '0;
+		pt_addr = '0;
+		pt_wrdata = '0;
+
+		unique case (state)
+			IDLE: rdy = '1;
+			INIT_BEGIN: i_en = i_rdy;
+			INIT: begin
+				s_wren = i_wren;
+				s_addr = i_addr;
+				s_wrdata = i_wrdata;
+			end
+			KSA_BEGIN: k_en = k_rdy;
+			KSA: begin
+				s_wren = k_wren;
+				s_addr = k_addr;
+				s_wrdata = k_wrdata;
+			end
+			PRGA_BEGIN: p_en = p_rdy;
+			PRGA: begin
+				s_wren = p_s_wren;
+				s_addr = p_s_addr;
+				s_wrdata = p_s_wrdata;
+				ct_addr = p_ct_addr;
+				pt_wren = p_pt_wren;
+				pt_addr = p_pt_addr;
+				pt_wrdata = p_pt_wrdata;
+			end
+			DONE: rdy = '1;
+			default: begin end
+		endcase
+	end: controller
+
+endmodule: arc4
diff --git a/src/competition.sv b/src/competition.sv
new file mode 100644
index 0000000..340359b
--- /dev/null
+++ b/src/competition.sv
@@ -0,0 +1,226 @@
+module competition (
+	input logic CLOCK_50,
+	input logic [3:0] KEY,
+	input logic [9:0] SW,
+
+	output logic [6:0] HEX0,
+	output logic [6:0] HEX1,
+	output logic [6:0] HEX2,
+	output logic [6:0] HEX3,
+	output logic [6:0] HEX4,
+	output logic [6:0] HEX5,
+	output logic [9:0] LEDR
+);
+
+	typedef enum logic [6:0] {
+		BLANK	= 7'b1111111,
+		DASH	= 7'b0111111,
+		ZERO	= 7'b1000000,
+		ONE	= 7'b1111001,
+		TWO	= 7'b0100100,
+		THREE	= 7'b0110000,
+		FOUR	= 7'b0011001,
+		FIVE	= 7'b0010010,
+		SIX	= 7'b0000010,
+		SEVEN	= 7'b1111000,
+		EIGHT	= 7'b0000000,
+		NINE	= 7'b0010000,
+		A	= 7'b0001000,
+		B	= 7'b0000011,
+		C	= 7'b1000110,
+		D	= 7'b0100001,
+		E	= 7'b0000110,
+		F	= 7'b0001110
+	} seven_seg_t;
+
+	logic clk, pll_locked, rst_n, en, rdy, key_valid;
+	logic [23:0] key;
+
+	logic [7:0] ct_addr;
+	logic [7:0] ct_rddata;
+
+	enum logic [1:0] {
+		IDLE,
+		CRACK,
+		DONE
+	} state;
+
+	pll sys_pll (
+		.refclk(CLOCK_50),
+		.rst(~KEY[3]),
+		.outclk_0(clk),
+		.locked(pll_locked)
+	);
+
+	assign rst_n = KEY[3] & pll_locked;
+	assign LEDR[0] = rdy;
+	assign LEDR[1] = key_valid;
+	assign LEDR[9:2] = '0;
+
+	ct_mem ct (
+		.address(ct_addr),
+		.clock(clk),
+		.data('0),
+		.wren('0),
+		.q(ct_rddata)
+	);
+
+	multicrack mc (
+		.clk,
+		.rst_n,
+		.en,
+		.rdy,
+		.key,
+		.key_valid,
+		.ct_addr,
+		.ct_rddata
+	);
+
+	always_ff @(posedge clk) begin
+		if (~rst_n) begin
+			state <= IDLE;
+		end else unique case (state)
+			IDLE: if (rdy) state <= CRACK;
+			CRACK: if (rdy) state <= DONE;
+			DONE: state <= DONE;
+		endcase
+	end
+
+	always_comb begin
+		if (state == IDLE && rdy) en = '1;
+		else en = '0;
+	end
+
+	always_comb begin: hex_disp
+		if (state != DONE) begin
+			HEX0 = BLANK;
+			HEX1 = BLANK;
+			HEX2 = BLANK;
+			HEX3 = BLANK;
+			HEX4 = BLANK;
+			HEX5 = BLANK;
+		end else if (~key_valid) begin
+			HEX0 = DASH;
+			HEX1 = DASH;
+			HEX2 = DASH;
+			HEX3 = DASH;
+			HEX4 = DASH;
+			HEX5 = DASH;
+		end else begin
+			unique case (key[23:20])
+				4'h0: HEX5 = ZERO;
+				4'h1: HEX5 = ONE;
+				4'h2: HEX5 = TWO;
+				4'h3: HEX5 = THREE;
+				4'h4: HEX5 = FOUR;
+				4'h5: HEX5 = FIVE;
+				4'h6: HEX5 = SIX;
+				4'h7: HEX5 = SEVEN;
+				4'h8: HEX5 = EIGHT;
+				4'h9: HEX5 = NINE;
+				4'hA: HEX5 = A;
+				4'hB: HEX5 = B;
+				4'hC: HEX5 = C;
+				4'hD: HEX5 = D;
+				4'hE: HEX5 = E;
+				4'hF: HEX5 = F;
+			endcase
+
+			unique case (key[19:16])
+				4'h0: HEX4 = ZERO;
+				4'h1: HEX4 = ONE;
+				4'h2: HEX4 = TWO;
+				4'h3: HEX4 = THREE;
+				4'h4: HEX4 = FOUR;
+				4'h5: HEX4 = FIVE;
+				4'h6: HEX4 = SIX;
+				4'h7: HEX4 = SEVEN;
+				4'h8: HEX4 = EIGHT;
+				4'h9: HEX4 = NINE;
+				4'hA: HEX4 = A;
+				4'hB: HEX4 = B;
+				4'hC: HEX4 = C;
+				4'hD: HEX4 = D;
+				4'hE: HEX4 = E;
+				4'hF: HEX4 = F;
+			endcase
+
+			unique case (key[15:12])
+				4'h0: HEX3 = ZERO;
+				4'h1: HEX3 = ONE;
+				4'h2: HEX3 = TWO;
+				4'h3: HEX3 = THREE;
+				4'h4: HEX3 = FOUR;
+				4'h5: HEX3 = FIVE;
+				4'h6: HEX3 = SIX;
+				4'h7: HEX3 = SEVEN;
+				4'h8: HEX3 = EIGHT;
+				4'h9: HEX3 = NINE;
+				4'hA: HEX3 = A;
+				4'hB: HEX3 = B;
+				4'hC: HEX3 = C;
+				4'hD: HEX3 = D;
+				4'hE: HEX3 = E;
+				4'hF: HEX3 = F;
+			endcase
+
+			unique case (key[11:8])
+				4'h0: HEX2 = ZERO;
+				4'h1: HEX2 = ONE;
+				4'h2: HEX2 = TWO;
+				4'h3: HEX2 = THREE;
+				4'h4: HEX2 = FOUR;
+				4'h5: HEX2 = FIVE;
+				4'h6: HEX2 = SIX;
+				4'h7: HEX2 = SEVEN;
+				4'h8: HEX2 = EIGHT;
+				4'h9: HEX2 = NINE;
+				4'hA: HEX2 = A;
+				4'hB: HEX2 = B;
+				4'hC: HEX2 = C;
+				4'hD: HEX2 = D;
+				4'hE: HEX2 = E;
+				4'hF: HEX2 = F;
+			endcase
+
+			unique case (key[7:4])
+				4'h0: HEX1 = ZERO;
+				4'h1: HEX1 = ONE;
+				4'h2: HEX1 = TWO;
+				4'h3: HEX1 = THREE;
+				4'h4: HEX1 = FOUR;
+				4'h5: HEX1 = FIVE;
+				4'h6: HEX1 = SIX;
+				4'h7: HEX1 = SEVEN;
+				4'h8: HEX1 = EIGHT;
+				4'h9: HEX1 = NINE;
+				4'hA: HEX1 = A;
+				4'hB: HEX1 = B;
+				4'hC: HEX1 = C;
+				4'hD: HEX1 = D;
+				4'hE: HEX1 = E;
+				4'hF: HEX1 = F;
+			endcase
+
+			unique case (key[3:0])
+				4'h0: HEX0 = ZERO;
+				4'h1: HEX0 = ONE;
+				4'h2: HEX0 = TWO;
+				4'h3: HEX0 = THREE;
+				4'h4: HEX0 = FOUR;
+				4'h5: HEX0 = FIVE;
+				4'h6: HEX0 = SIX;
+				4'h7: HEX0 = SEVEN;
+				4'h8: HEX0 = EIGHT;
+				4'h9: HEX0 = NINE;
+				4'hA: HEX0 = A;
+				4'hB: HEX0 = B;
+				4'hC: HEX0 = C;
+				4'hD: HEX0 = D;
+				4'hE: HEX0 = E;
+				4'hF: HEX0 = F;
+			endcase
+		end
+	end: hex_disp
+
+endmodule: competition
diff --git a/src/crack.sv b/src/crack.sv
new file mode 100644
index 0000000..44bdac4
--- /dev/null
+++ b/src/crack.sv
@@ -0,0 +1,126 @@
+module crack #(
+	parameter logic [23:0] KeyStart = '0,
+	parameter logic [23:0] KeyIncrement = 24'd1
+) (
+	input logic clk,
+	input logic rst_n,
+	input logic en,
+	output logic rdy,
+	output logic [23:0] key,
+	output logic key_valid,
+	output logic [7:0] ct_addr,
+	input logic [7:0] ct_rddata,
+	input logic [7:0] pt_addr_ext,
+	output logic [7:0] pt_rddata_ext
+);
+
+	logic is_printable;
+	logic [23:0] key_d, key_q;
+
+	logic a4_rst_n, a4_en, a4_rdy;
+
+	logic pt_wren;
+	logic [7:0] pt_addr, pt_addr_mem;
+	logic [7:0] pt_wrdata, pt_rddata;
+
+	enum logic [2:0] {
+		INIT,
+		ARC4_INIT,
+		ARC4_RDY,
+		ARC4,
+		NOT_FOUND,
+		FOUND
+	} state_d, state_q;
+
+	pt_core_mem pt (
+		.address(pt_addr_mem),
+		.clock(clk),
+		.data(pt_wrdata),
+		.wren(pt_wren),
+		.q(pt_rddata)
+	);
+
+	arc4 a4 (
+		.clk,
+		.rst_n(rst_n & a4_rst_n),
+		.en(a4_en),
+		.rdy(a4_rdy),
+		.key,
+		.ct_addr,
+		.ct_rddata,
+		.pt_addr,
+		.pt_rddata,
+		.pt_wrdata,
+		.pt_wren
+	);
+
+	assign key = key_q;
+	assign pt_rddata_ext = pt_rddata;
+	assign pt_addr_mem = ((state_q == FOUND) || (state_q == NOT_FOUND)) ? pt_addr_ext : pt_addr;
+
+	assign is_printable = (pt_wrdata >= 8'h20) && (pt_wrdata <= 8'h7E);
+
+	always_ff @(posedge clk) begin
+		if (~rst_n) begin
+			state_q <= INIT;
+			key_q <= KeyStart;
+		end else begin
+			state_q <= state_d;
+			key_q <= key_d;
+		end
+	end
+
+	always_comb unique case (state_q)
+		INIT:
+			if (en) state_d = ARC4_INIT;
+			else state_d = INIT;
+		ARC4_INIT: state_d = ARC4_RDY;
+		ARC4_RDY: begin
+			if (a4_rdy) state_d = ARC4;
+			else state_d = ARC4_RDY;
+		end
+		ARC4: begin
+			state_d = ARC4;
+			if (a4_rdy) state_d = FOUND;
+			else if (pt_wren && (pt_addr != '0)) begin
+				if (~is_printable) begin
+					if (key_q == '1) state_d = NOT_FOUND;
+					else state_d = ARC4_INIT;
+				end
+			end
+		end
+		NOT_FOUND: state_d = NOT_FOUND;
+		FOUND: state_d = FOUND;
+		default: begin end
+	endcase
+
+	always_comb begin
+		rdy = '0;
+		key_valid = '0;
+
+		a4_rst_n = '1;
+		a4_en = '0;
+
+		key_d = key_q;
+
+		unique case (state_q)
+			INIT: rdy = '1;
+			ARC4_INIT: a4_rst_n = '0;
+			ARC4_RDY: a4_en = a4_rdy;
+			ARC4: begin
+				if (~a4_rdy && pt_wren && (pt_addr != '0)) begin
+					if (~is_printable) begin
+						key_d = key_q + KeyIncrement;
+					end
+				end
+			end
+			NOT_FOUND: rdy = '1;
+			FOUND: begin
+				rdy = '1;
+				key_valid = '1;
+			end
+			default: begin end
+		endcase
+	end
+
+endmodule: crack
diff --git a/src/ct_core_mem.v b/src/ct_core_mem.v
new file mode 100644
index 0000000..293081e
--- /dev/null
+++ b/src/ct_core_mem.v
@@ -0,0 +1,67 @@
+module ct_core_mem (
+	address,
+	clock,
+	data,
+	wren,
+	q
+);
+
+	input [7:0] address;
+	input clock;
+	input [7:0] data;
+	input wren;
+	output [7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1 clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram altsyncram_component (
+		.address_a(address),
+		.clock0(clock),
+		.data_a(data),
+		.wren_a(wren),
+		.q_a(sub_wire0),
+		.aclr0(1'b0),
+		.aclr1(1'b0),
+		.address_b(1'b1),
+		.addressstall_a(1'b0),
+		.addressstall_b(1'b0),
+		.byteena_a(1'b1),
+		.byteena_b(1'b1),
+		.clock1(1'b1),
+		.clocken0(1'b1),
+		.clocken1(1'b1),
+		.clocken2(1'b1),
+		.clocken3(1'b1),
+		.data_b(1'b1),
+		.eccstatus(),
+		.q_b(),
+		.rden_a(1'b1),
+		.rden_b(1'b1),
+		.wren_b(1'b0)
+	);
+	defparam
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "message.mif",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
diff --git a/src/ct_mem.qip b/src/ct_mem.qip
new file mode 100644
index 0000000..fc31acd
--- /dev/null
+++ b/src/ct_mem.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"

+set_global_assignment -name IP_TOOL_VERSION "24.1"

+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"

+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ct_mem.v"]

+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ct_mem_bb.v"]

diff --git a/src/ct_mem.v b/src/ct_mem.v
new file mode 100644
index 0000000..37c8b80
--- /dev/null
+++ b/src/ct_mem.v
@@ -0,0 +1,177 @@
+// megafunction wizard: %RAM: 1-PORT%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: altsyncram

+

+// ============================================================

+// File Name: ct_mem.v

+// Megafunction Name(s):

+// 			altsyncram

+//

+// Simulation Library Files(s):

+// 			altera_mf

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition

+// ************************************************************

+

+

+//Copyright (C) 2025  Altera Corporation. All rights reserved.

+//Your use of Altera Corporation's design tools, logic functions

+//and other software and tools, and any partner logic

+//functions, and any output files from any of the foregoing

+//(including device programming or simulation files), and any

+//associated documentation or information are expressly subject

+//to the terms and conditions of the Altera Program License

+//Subscription Agreement, the Altera Quartus Prime License Agreement,

+//the Altera IP License Agreement, or other applicable license

+//agreement, including, without limitation, that your use is for

+//the sole purpose of programming logic devices manufactured by

+//Altera and sold by Altera or its authorized distributors.  Please

+//refer to the Altera Software License Subscription Agreements

+//on the Quartus Prime software download page.

+

+

+// synopsys translate_off

+`timescale 1 ps / 1 ps

+// synopsys translate_on

+module ct_mem (

+	address,

+	clock,

+	data,

+	wren,

+	q);

+

+	input	[7:0]  address;

+	input	  clock;

+	input	[7:0]  data;

+	input	  wren;

+	output	[7:0]  q;

+`ifndef ALTERA_RESERVED_QIS

+// synopsys translate_off

+`endif

+	tri1	  clock;

+`ifndef ALTERA_RESERVED_QIS

+// synopsys translate_on

+`endif

+

+	wire [7:0] sub_wire0;

+	wire [7:0] q = sub_wire0[7:0];

+

+	altsyncram	altsyncram_component (

+				.address_a (address),

+				.clock0 (clock),

+				.data_a (data),

+				.wren_a (wren),

+				.q_a (sub_wire0),

+				.aclr0 (1'b0),

+				.aclr1 (1'b0),

+				.address_b (1'b1),

+				.addressstall_a (1'b0),

+				.addressstall_b (1'b0),

+				.byteena_a (1'b1),

+				.byteena_b (1'b1),

+				.clock1 (1'b1),

+				.clocken0 (1'b1),

+				.clocken1 (1'b1),

+				.clocken2 (1'b1),

+				.clocken3 (1'b1),

+				.data_b (1'b1),

+				.eccstatus (),

+				.q_b (),

+				.rden_a (1'b1),

+				.rden_b (1'b1),

+				.wren_b (1'b0));

+	defparam

+		altsyncram_component.clock_enable_input_a = "BYPASS",

+		altsyncram_component.clock_enable_output_a = "BYPASS",

+		altsyncram_component.init_file = "message.mif",

+		altsyncram_component.intended_device_family = "Cyclone V",

+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CT",

+		altsyncram_component.lpm_type = "altsyncram",

+		altsyncram_component.numwords_a = 256,

+		altsyncram_component.operation_mode = "SINGLE_PORT",

+		altsyncram_component.outdata_aclr_a = "NONE",

+		altsyncram_component.outdata_reg_a = "UNREGISTERED",

+		altsyncram_component.power_up_uninitialized = "FALSE",

+		altsyncram_component.ram_block_type = "M10K",

+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",

+		altsyncram_component.widthad_a = 8,

+		altsyncram_component.width_a = 8,

+		altsyncram_component.width_byteena_a = 1;

+

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"

+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"

+// Retrieval info: PRIVATE: AclrData NUMERIC "0"

+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"

+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"

+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"

+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

+// Retrieval info: PRIVATE: Clken NUMERIC "0"

+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"

+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"

+// Retrieval info: PRIVATE: JTAG_ID STRING "CT"

+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

+// Retrieval info: PRIVATE: MIFfilename STRING "message.mif"

+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"

+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"

+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"

+// Retrieval info: PRIVATE: RegData NUMERIC "1"

+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"

+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"

+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"

+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"

+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"

+// Retrieval info: PRIVATE: WidthData NUMERIC "8"

+// Retrieval info: PRIVATE: rden NUMERIC "0"

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"

+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"

+// Retrieval info: CONSTANT: INIT_FILE STRING "test2.mif"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CT"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"

+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"

+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"

+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"

+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"

+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"

+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"

+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"

+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"

+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"

+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"

+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"

+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0

+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0

+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0

+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem.inc FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem.cmp FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem.bsf FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem_inst.v FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL ct_mem_bb.v TRUE

+// Retrieval info: LIB_FILE: altera_mf

diff --git a/src/init.sv b/src/init.sv
new file mode 100644
index 0000000..ae42634
--- /dev/null
+++ b/src/init.sv
@@ -0,0 +1,27 @@
+module init(clk, rst_n, en, rdy, addr, wrdata, wren);
+
+	input logic clk, rst_n, en;
+	output logic rdy, wren;
+	output logic [7:0] addr, wrdata;
+
+	always_ff @(posedge clk) begin
+		if (~rst_n) begin
+			rdy <= 1'b1;
+			wren <= 1'b0;
+			addr <= 8'b0;
+			wrdata <= 8'b0;
+		end else if (rdy && en) begin
+			rdy <= 1'b0;
+			wren <= 1'b1;
+		end else if (wren && ((wrdata + 1'b1) !== 8'b0)) begin
+			addr <= addr + 1;
+			wrdata <= wrdata + 1;
+		end else if (wren && ((wrdata + 1'b1) == 8'b0)) begin
+			rdy <= 1'b1;
+			wren <= 1'b0;
+			addr <= 8'b0;
+			wrdata <= 8'b0;
+		end
+	end
+
+endmodule: init
diff --git a/src/ksa.sv b/src/ksa.sv
new file mode 100644
index 0000000..0d79899
--- /dev/null
+++ b/src/ksa.sv
@@ -0,0 +1,86 @@
+module ksa(clk, rst_n, en, rdy, key, addr, rddata, wrdata, wren);
+
+	input logic clk, rst_n, en;
+	input logic [7:0] rddata;
+	input logic [23:0] key;
+	output logic rdy, wren;
+	output logic [7:0] addr, wrdata;
+
+	logic started, wren_next;
+	logic [2:0] state, state_next;
+	logic [7:0] i, j, i_next, j_next, wrdata_next, addr_next, si, si_next;
+
+	always_comb begin: ksa_logic
+		state_next = state + 1;
+		i_next = i;
+		j_next = j;
+		addr_next = i;
+		wrdata_next = 8'b0;
+		wren_next = 1'b0;
+		si_next = si;
+		case (state)
+			/* Fetch s[i]. */
+			3'd0: begin end
+			/* s[i] is now in rddata. */
+			3'd1: begin end
+			/* Compute j; fetch s[j]; latch s[i] from rddata. */
+			3'd2: begin
+				if (i % 3 == 2'd0)
+					j_next = j + rddata + key[23:16];
+				else if (i % 3 == 2'd1)
+					j_next = j + rddata + key[15:8];
+				else
+					j_next = j + rddata + key[7:0];
+				addr_next = j_next;
+				si_next = rddata;
+			end
+			/* s[j] is now in rddata. */
+			3'd3: begin end
+			/* Store rddata (s[j]) to address i. */
+			3'd4: begin
+				wrdata_next = rddata;
+				wren_next = 1'b1;
+			end
+			/* Store si (s[i]) to address j; increment i; reset. */
+			3'd5: begin
+				state_next = 3'd0;
+				i_next = i + 1;
+				addr_next = j;
+				wrdata_next = si;
+				wren_next = 1'b1;
+			end
+		endcase
+	end: ksa_logic
+
+	always_ff @(posedge clk) begin: ksa_state_machine
+		if (~rst_n) begin
+			rdy <= 1'b1;
+			started <= 1'b0;
+			state <= 3'd0;
+			i <= 8'b0;
+			j <= 8'b0;
+			addr <= 8'b0;
+		end else if (rdy && en) begin
+			rdy <= 1'b0;
+			started <= 1'b1;
+			state <= 3'd0;
+			i <= 8'b0;
+			j <= 8'b0;
+			addr <= 8'b0;
+			wren <= 1'b0;
+		end else if (started) begin
+			state <= state_next;
+			i <= i_next;
+			j <= j_next;
+			addr <= addr_next;
+			wrdata <= wrdata_next;
+			wren <= wren_next;
+			si <= si_next;
+			if ((i == 8'd255) && (state == 3'd5)) begin
+				rdy <= 1'b1;
+				started <= 1'b0;
+			end
+		end
+	end: ksa_state_machine
+
+endmodule: ksa
diff --git a/src/message.mif b/src/message.mif
new file mode 100644
index 0000000..f119cfd
--- /dev/null
+++ b/src/message.mif
@@ -0,0 +1,264 @@
+WIDTH=8;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+00 : 4A;
+01 : 7A;
+02 : 86;
+03 : 5E;
+04 : 5F;
+05 : 34;
+06 : 30;
+07 : 55;
+08 : 98;
+09 : 58;
+0A : BD;
+0B : 78;
+0C : BC;
+0D : 39;
+0E : 6F;
+0F : 61;
+10 : 10;
+11 : 95;
+12 : 83;
+13 : 28;
+14 : BE;
+15 : 14;
+16 : 23;
+17 : 75;
+18 : CE;
+19 : 76;
+1A : 1B;
+1B : BD;
+1C : 05;
+1D : 11;
+1E : C4;
+1F : 8B;
+20 : 53;
+21 : A0;
+22 : 16;
+23 : 7A;
+24 : C1;
+25 : E1;
+26 : 7A;
+27 : D8;
+28 : 44;
+29 : 2A;
+2A : C2;
+2B : 6B;
+2C : 1B;
+2D : 6D;
+2E : 36;
+2F : B8;
+30 : 86;
+31 : 67;
+32 : DB;
+33 : C8;
+34 : 33;
+35 : A2;
+36 : 41;
+37 : 03;
+38 : 9E;
+39 : 4C;
+3A : 29;
+3B : 0A;
+3C : 20;
+3D : 90;
+3E : 33;
+3F : 39;
+40 : 56;
+41 : 0F;
+42 : 37;
+43 : B2;
+44 : 17;
+45 : E2;
+46 : 8C;
+47 : 55;
+48 : 6F;
+49 : 84;
+4A : B4;
+4B : 00;
+4C : 00;
+4D : 00;
+4E : 00;
+4F : 00;
+50 : 00;
+51 : 00;
+52 : 00;
+53 : 00;
+54 : 00;
+55 : 00;
+56 : 00;
+57 : 00;
+58 : 00;
+59 : 00;
+5A : 00;
+5B : 00;
+5C : 00;
+5D : 00;
+5E : 00;
+5F : 00;
+60 : 00;
+61 : 00;
+62 : 00;
+63 : 00;
+64 : 00;
+65 : 00;
+66 : 00;
+67 : 00;
+68 : 00;
+69 : 00;
+6A : 00;
+6B : 00;
+6C : 00;
+6D : 00;
+6E : 00;
+6F : 00;
+70 : 00;
+71 : 00;
+72 : 00;
+73 : 00;
+74 : 00;
+75 : 00;
+76 : 00;
+77 : 00;
+78 : 00;
+79 : 00;
+7A : 00;
+7B : 00;
+7C : 00;
+7D : 00;
+7E : 00;
+7F : 00;
+80 : 00;
+81 : 00;
+82 : 00;
+83 : 00;
+84 : 00;
+85 : 00;
+86 : 00;
+87 : 00;
+88 : 00;
+89 : 00;
+8A : 00;
+8B : 00;
+8C : 00;
+8D : 00;
+8E : 00;
+8F : 00;
+90 : 00;
+91 : 00;
+92 : 00;
+93 : 00;
+94 : 00;
+95 : 00;
+96 : 00;
+97 : 00;
+98 : 00;
+99 : 00;
+9A : 00;
+9B : 00;
+9C : 00;
+9D : 00;
+9E : 00;
+9F : 00;
+A0 : 00;
+A1 : 00;
+A2 : 00;
+A3 : 00;
+A4 : 00;
+A5 : 00;
+A6 : 00;
+A7 : 00;
+A8 : 00;
+A9 : 00;
+AA : 00;
+AB : 00;
+AC : 00;
+AD : 00;
+AE : 00;
+AF : 00;
+B0 : 00;
+B1 : 00;
+B2 : 00;
+B3 : 00;
+B4 : 00;
+B5 : 00;
+B6 : 00;
+B7 : 00;
+B8 : 00;
+B9 : 00;
+BA : 00;
+BB : 00;
+BC : 00;
+BD : 00;
+BE : 00;
+BF : 00;
+C0 : 00;
+C1 : 00;
+C2 : 00;
+C3 : 00;
+C4 : 00;
+C5 : 00;
+C6 : 00;
+C7 : 00;
+C8 : 00;
+C9 : 00;
+CA : 00;
+CB : 00;
+CC : 00;
+CD : 00;
+CE : 00;
+CF : 00;
+D0 : 00;
+D1 : 00;
+D2 : 00;
+D3 : 00;
+D4 : 00;
+D5 : 00;
+D6 : 00;
+D7 : 00;
+D8 : 00;
+D9 : 00;
+DA : 00;
+DB : 00;
+DC : 00;
+DD : 00;
+DE : 00;
+DF : 00;
+E0 : 00;
+E1 : 00;
+E2 : 00;
+E3 : 00;
+E4 : 00;
+E5 : 00;
+E6 : 00;
+E7 : 00;
+E8 : 00;
+E9 : 00;
+EA : 00;
+EB : 00;
+EC : 00;
+ED : 00;
+EE : 00;
+EF : 00;
+F0 : 00;
+F1 : 00;
+F2 : 00;
+F3 : 00;
+F4 : 00;
+F5 : 00;
+F6 : 00;
+F7 : 00;
+F8 : 00;
+F9 : 00;
+FA : 00;
+FB : 00;
+FC : 00;
+FD : 00;
+FE : 00;
+FF : 00;
+END;
diff --git a/src/multicrack.sv b/src/multicrack.sv
new file mode 100644
index 0000000..c3f1aef
--- /dev/null
+++ b/src/multicrack.sv
@@ -0,0 +1,226 @@
+module multicrack (
+	input logic clk,
+	input logic rst_n,
+	input logic en,
+	output logic rdy,
+	output logic [23:0] key,
+	output logic key_valid,
+	output logic [7:0] ct_addr,
+	input logic [7:0] ct_rddata
+);
+
+	localparam int NUM_CORES = 108;
+	localparam int WINNER_W = $clog2(NUM_CORES);
+	localparam logic [23:0] KEY_INCREMENT = 24'd108;
+
+	logic c_en;
+
+	logic [NUM_CORES-1:0] core_rdy, core_key_valid;
+	logic [NUM_CORES-1:0][7:0] core_ct_addr;
+	logic [NUM_CORES-1:0][7:0] core_pt_addr;
+	logic [NUM_CORES-1:0][7:0] core_pt_rddata;
+	logic [NUM_CORES-1:0][23:0] core_key;
+
+	logic [NUM_CORES-1:0] ct_core_wren;
+	logic [NUM_CORES-1:0][7:0] ct_core_addr;
+	logic [NUM_CORES-1:0][7:0] ct_core_wrdata, ct_core_rddata;
+
+	logic pt_wren;
+	logic [7:0] pt_addr;
+	logic [7:0] pt_wrdata, pt_rddata;
+
+	logic [7:0] ct_copy_idx_d, ct_copy_idx_q;
+	logic [7:0] pt_copy_idx_d, pt_copy_idx_q;
+	logic [WINNER_W-1:0] winner_d, winner_q;
+
+	logic all_cores_rdy;
+	logic winning_core_valid;
+	logic [WINNER_W-1:0] winning_core_idx;
+	logic [23:0] winner_key;
+	logic [7:0] winner_pt_rddata;
+
+	typedef enum logic [2:0] {
+		IDLE,
+		CT_FETCH,
+		CT_WRITE,
+		CRACK_START,
+		CRACK,
+		PT_FETCH,
+		PT_WRITE,
+		DONE
+	} state_t;
+
+	state_t state_d, state_q;
+
+	pt_mem pt (
+		.address(pt_addr),
+		.clock(clk),
+		.data(pt_wrdata),
+		.wren(pt_wren),
+		.q(pt_rddata)
+	);
+
+	genvar i;
+	generate
+		for (i = 0; i < NUM_CORES; i++) begin : gen_cores
+			ct_core_mem ct (
+				.address(ct_core_addr[i]),
+				.clock(clk),
+				.data(ct_core_wrdata[i]),
+				.wren(ct_core_wren[i]),
+				.q(ct_core_rddata[i])
+			);
+
+			crack #(
+				.KeyStart(i),
+				.KeyIncrement(KEY_INCREMENT)
+			) core (
+				.clk,
+				.rst_n,
+				.en(c_en),
+				.rdy(core_rdy[i]),
+				.key(core_key[i]),
+				.key_valid(core_key_valid[i]),
+				.ct_addr(core_ct_addr[i]),
+				.ct_rddata(ct_core_rddata[i]),
+				.pt_addr_ext(core_pt_addr[i]),
+				.pt_rddata_ext(core_pt_rddata[i])
+			);
+		end
+	endgenerate
+
+	always_comb begin
+		all_cores_rdy = 1'b1;
+		winning_core_valid = 1'b0;
+		winning_core_idx = '0;
+
+		for (int j = 0; j < NUM_CORES; j++) begin
+			all_cores_rdy &= core_rdy[j];
+			if (!winning_core_valid && core_rdy[j] && core_key_valid[j]) begin
+				winning_core_valid = 1'b1;
+				winning_core_idx = WINNER_W'(j);
+			end
+		end
+	end
+
+	assign winner_key = core_key[winner_q];
+	assign winner_pt_rddata = core_pt_rddata[winner_q];
+
+	always_ff @(posedge clk) begin
+		if (~rst_n) begin
+			state_q <= IDLE;
+			ct_copy_idx_q <= '0;
+			pt_copy_idx_q <= '0;
+			winner_q <= '0;
+		end else begin
+			state_q <= state_d;
+			ct_copy_idx_q <= ct_copy_idx_d;
+			pt_copy_idx_q <= pt_copy_idx_d;
+			winner_q <= winner_d;
+		end
+	end
+
+	always_comb begin
+		state_d = state_q;
+		ct_copy_idx_d = ct_copy_idx_q;
+		pt_copy_idx_d = pt_copy_idx_q;
+		winner_d = winner_q;
+
+		unique case (state_q)
+			IDLE: begin
+				if (en) begin
+					state_d = CT_FETCH;
+					ct_copy_idx_d = '0;
+					pt_copy_idx_d = '0;
+					winner_d = '0;
+				end
+			end
+			CT_FETCH: state_d = CT_WRITE;
+			CT_WRITE: begin
+				if (ct_copy_idx_q == 8'hFF) begin
+					state_d = CRACK_START;
+				end else begin
+					state_d = CT_FETCH;
+					ct_copy_idx_d = ct_copy_idx_q + 8'd1;
+				end
+			end
+			CRACK_START: begin
+				if (all_cores_rdy) state_d = CRACK;
+			end
+			CRACK: begin
+				if (winning_core_valid) begin
+					state_d = PT_FETCH;
+					pt_copy_idx_d = '0;
+					winner_d = winning_core_idx;
+				end else if (all_cores_rdy) begin
+					state_d = DONE;
+				end
+			end
+			PT_FETCH: state_d = PT_WRITE;
+			PT_WRITE: begin
+				if (pt_copy_idx_q == 8'hFF) begin
+					state_d = DONE;
+				end else begin
+					state_d = PT_FETCH;
+					pt_copy_idx_d = pt_copy_idx_q + 8'd1;
+				end
+			end
+			DONE: state_d = DONE;
+			default: state_d = IDLE;
+		endcase
+	end
+
+	always_comb begin
+		rdy = '0;
+		key_valid = '0;
+		key = '0;
+
+		c_en = '0;
+
+		ct_addr = '0;
+
+		pt_addr = '0;
+		pt_wrdata = '0;
+		pt_wren = '0;
+
+		for (int j = 0; j < NUM_CORES; j++) begin
+			ct_core_addr[j] = core_ct_addr[j];
+			ct_core_wrdata[j] = '0;
+			ct_core_wren[j] = '0;
+			core_pt_addr[j] = pt_copy_idx_q;
+		end
+
+		unique case (state_q)
+			IDLE: rdy = '1;
+			CT_FETCH: begin
+				ct_addr = ct_copy_idx_q;
+			end
+			CT_WRITE: begin
+				for (int j = 0; j < NUM_CORES; j++) begin
+					ct_core_addr[j] = ct_copy_idx_q;
+					ct_core_wrdata[j] = ct_rddata;
+					ct_core_wren[j] = '1;
+				end
+			end
+			CRACK_START: begin
+				c_en = all_cores_rdy;
+			end
+			CRACK: begin end
+			PT_FETCH: begin end
+			PT_WRITE: begin
+				pt_addr = pt_copy_idx_q;
+				pt_wren = '1;
+				pt_wrdata = winner_pt_rddata;
+			end
+			DONE: begin
+				rdy = '1;
+				if (core_key_valid[winner_q]) begin
+					key_valid = '1;
+					key = winner_key;
+				end
+			end
+			default: begin end
+		endcase
+	end
+
+endmodule: multicrack
diff --git a/src/pll.v b/src/pll.v
new file mode 100644
index 0000000..4d1b780
--- /dev/null
+++ b/src/pll.v
@@ -0,0 +1,253 @@
+// megafunction wizard: %PLL Intel FPGA IP v24.1%

+// GENERATION: XML

+// pll.v

+

+// Generated using ACDS version 24.1 1077

+

+`timescale 1 ps / 1 ps

+module pll (

+		input  wire  refclk,   //  refclk.clk

+		input  wire  rst,      //   reset.reset

+		output wire  outclk_0, // outclk0.clk

+		output wire  locked    //  locked.export

+	);

+

+	pll_0002 pll_inst (

+		.refclk   (refclk),   //  refclk.clk

+		.rst      (rst),      //   reset.reset

+		.outclk_0 (outclk_0), // outclk0.clk

+		.locked   (locked)    //  locked.export

+	);

+

+endmodule

+// Retrieval info: <?xml version="1.0"?>

+//<!--

+//	Generated by Altera MegaWizard Launcher Utility version 1.0

+//	************************************************************

+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//	************************************************************

+//	Copyright (C) 1991-2026 Altera Corporation

+//	Any megafunction design, and related net list (encrypted or decrypted),

+//	support information, device programming or simulation file, and any other

+//	associated documentation or information provided by Altera or a partner

+//	under Altera's Megafunction Partnership Program may be used only to

+//	program PLD devices (but not masked PLD devices) from Altera.  Any other

+//	use of such megafunction design, net list, support information, device

+//	programming or simulation file, or any other related documentation or

+//	information is prohibited for any other purpose, including, but not

+//	limited to modification, reverse engineering, de-compiling, or use with

+//	any other silicon devices, unless such use is explicitly licensed under

+//	a separate agreement with Altera or a megafunction partner.  Title to

+//	the intellectual property, including patents, copyrights, trademarks,

+//	trade secrets, or maskworks, embodied in any such megafunction design,

+//	net list, support information, device programming or simulation file, or

+//	any other related documentation or information provided by Altera or a

+//	megafunction partner, remains with Altera, the megafunction partner, or

+//	their respective licensors.  No other licenses, including any licenses

+//	needed under any third party's intellectual property, are provided herein.

+//-->

+// Retrieval info: <instance entity-name="altera_pll" version="24.1" >

+// Retrieval info: 	<generic name="debug_print_output" value="false" />

+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />

+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />

+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />

+// Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />

+// Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />

+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />

+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />

+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />

+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />

+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />

+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />

+// Retrieval info: 	<generic name="gui_use_locked" value="true" />

+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />

+// Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />

+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />

+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />

+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />

+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="94.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />

+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />

+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />

+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />

+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />

+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />

+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />

+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />

+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />

+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />

+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />

+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />

+// Retrieval info: 	<generic name="gui_en_reconf" value="false" />

+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />

+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />

+// Retrieval info: 	<generic name="gui_phout_division" value="1" />

+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />

+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />

+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />

+// Retrieval info: 	<generic name="gui_dps_num" value="1" />

+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />

+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />

+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />

+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />

+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />

+// Retrieval info: 	<generic name="gui_active_clk" value="false" />

+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />

+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />

+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />

+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />

+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />

+// Retrieval info: </instance>

+// IPFS_FILES : pll.vo

+// RELATED_FILES: pll.v, pll_0002.v

diff --git a/src/pll_002.v b/src/pll_002.v
new file mode 100644
index 0000000..5a5d43b
--- /dev/null
+++ b/src/pll_002.v
@@ -0,0 +1,86 @@
+`timescale 1ns/10ps

+module  pll_0002(

+

+	// interface 'refclk'

+	input wire refclk,

+

+	// interface 'reset'

+	input wire rst,

+

+	// interface 'outclk0'

+	output wire outclk_0,

+

+	// interface 'locked'

+	output wire locked

+);

+

+	altera_pll #(

+		.fractional_vco_multiplier("false"),

+		.reference_clock_frequency("50.0 MHz"),

+		.operation_mode("direct"),

+		.number_of_clocks(1),

+		.output_clock_frequency0("94.000000 MHz"),

+		.phase_shift0("0 ps"),

+		.duty_cycle0(50),

+		.output_clock_frequency1("0 MHz"),

+		.phase_shift1("0 ps"),

+		.duty_cycle1(50),

+		.output_clock_frequency2("0 MHz"),

+		.phase_shift2("0 ps"),

+		.duty_cycle2(50),

+		.output_clock_frequency3("0 MHz"),

+		.phase_shift3("0 ps"),

+		.duty_cycle3(50),

+		.output_clock_frequency4("0 MHz"),

+		.phase_shift4("0 ps"),

+		.duty_cycle4(50),

+		.output_clock_frequency5("0 MHz"),

+		.phase_shift5("0 ps"),

+		.duty_cycle5(50),

+		.output_clock_frequency6("0 MHz"),

+		.phase_shift6("0 ps"),

+		.duty_cycle6(50),

+		.output_clock_frequency7("0 MHz"),

+		.phase_shift7("0 ps"),

+		.duty_cycle7(50),

+		.output_clock_frequency8("0 MHz"),

+		.phase_shift8("0 ps"),

+		.duty_cycle8(50),

+		.output_clock_frequency9("0 MHz"),

+		.phase_shift9("0 ps"),

+		.duty_cycle9(50),

+		.output_clock_frequency10("0 MHz"),

+		.phase_shift10("0 ps"),

+		.duty_cycle10(50),

+		.output_clock_frequency11("0 MHz"),

+		.phase_shift11("0 ps"),

+		.duty_cycle11(50),

+		.output_clock_frequency12("0 MHz"),

+		.phase_shift12("0 ps"),

+		.duty_cycle12(50),

+		.output_clock_frequency13("0 MHz"),

+		.phase_shift13("0 ps"),

+		.duty_cycle13(50),

+		.output_clock_frequency14("0 MHz"),

+		.phase_shift14("0 ps"),

+		.duty_cycle14(50),

+		.output_clock_frequency15("0 MHz"),

+		.phase_shift15("0 ps"),

+		.duty_cycle15(50),

+		.output_clock_frequency16("0 MHz"),

+		.phase_shift16("0 ps"),

+		.duty_cycle16(50),

+		.output_clock_frequency17("0 MHz"),

+		.phase_shift17("0 ps"),

+		.duty_cycle17(50),

+		.pll_type("General"),

+		.pll_subtype("General")

+	) altera_pll_i (

+		.rst	(rst),

+		.outclk	({outclk_0}),

+		.locked	(locked),

+		.fboutclk	( ),

+		.fbclk	(1'b0),

+		.refclk	(refclk)

+	);

+endmodule

diff --git a/src/prga.sv b/src/prga.sv
new file mode 100644
index 0000000..57f326f
--- /dev/null
+++ b/src/prga.sv
@@ -0,0 +1,228 @@
+module prga (
+	input logic clk,
+	input logic rst_n,
+	input logic en,
+	output logic rdy,
+	input logic [23:0] key,
+
+	output logic [7:0] s_addr,
+	input logic [7:0] s_rddata,
+	output logic [7:0] s_wrdata,
+	output logic s_wren,
+
+	output logic [7:0] ct_addr,
+	input logic [7:0] ct_rddata,
+
+	output logic [7:0] pt_addr,
+	input logic [7:0] pt_rddata,
+	output logic [7:0] pt_wrdata,
+	output logic pt_wren
+);
+
+	logic [7:0] i_d, i_q, j_d, j_q, k_d, k_q, si_d, si_q, sj_d, sj_q;
+	logic [7:0] length_d, length_q;
+
+	enum logic [3:0] {
+		INIT,
+		SET_LENGTH,
+		FETCH_I,
+		FETCH_J,
+		WRITE_I,
+		WRITE_J,
+		FETCH_PAD,
+		WRITE_PT,
+		DONE
+	} state_d, state_q;
+
+	always_comb begin: fsm_output_logic
+		rdy = '0;
+
+		i_d = i_q;
+		j_d = j_q;
+		k_d = k_q;
+		si_d = si_q;
+		sj_d = sj_q;
+		length_d = length_q;
+
+		unique case (state_q)
+			INIT: begin
+				rdy = '1;
+
+				s_addr = '0;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				/* Fetch message length. */
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			SET_LENGTH: begin
+				length_d = ct_rddata;
+
+				rdy = '0;
+
+				s_addr = '0;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = ct_rddata;
+				pt_wren = '1;
+			end
+			FETCH_I: begin
+				i_d = i_q + 1'b1;
+
+				rdy = '0;
+
+				s_addr = i_d;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			/* s_rddata now contains s[i]. */
+			FETCH_J: begin
+				/* Calculate j. */
+				j_d = j_q + s_rddata;
+
+				/* Save s[i]. */
+				si_d = s_rddata;
+
+				rdy = '0;
+
+				s_addr = j_d;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			/* s_rddata now contains s[j]. */
+			WRITE_I: begin
+				/* Save s[j]. */
+				sj_d = s_rddata;
+
+				rdy = '0;
+
+				s_addr = j_d;
+				s_wrdata = si_q;
+				s_wren = '1;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			WRITE_J: begin
+				rdy = '0;
+
+				s_addr = i_d;
+				s_wrdata = sj_q;
+				s_wren = '1;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			FETCH_PAD: begin
+				rdy = '0;
+
+				s_addr = si_q + sj_q;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = k_q;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			WRITE_PT: begin
+				k_d = k_q + 1'b1;
+
+				rdy = '0;
+
+				s_addr = '0;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = '0;
+
+				pt_addr = k_q;
+				pt_wrdata = s_rddata ^ ct_rddata;
+				pt_wren = '1;
+			end
+			DONE: begin
+				rdy = '1;
+
+				s_addr = '0;
+				s_wrdata = '0;
+				s_wren = '0;
+
+				ct_addr = '0;
+
+				pt_addr = '0;
+				pt_wrdata = '0;
+				pt_wren = '0;
+			end
+			default: begin end
+		endcase
+	end: fsm_output_logic
+
+	always_comb begin: fsm_next_state_logic
+		unique case (state_q)
+			INIT: begin
+				if (rdy && en) state_d = SET_LENGTH;
+				else state_d = INIT;
+			end
+			SET_LENGTH: state_d = FETCH_I;
+			FETCH_I: state_d = FETCH_J;
+			FETCH_J: state_d = WRITE_I;
+			WRITE_I: state_d = WRITE_J;
+			WRITE_J: state_d = FETCH_PAD;
+			FETCH_PAD: state_d = WRITE_PT;
+			WRITE_PT: begin
+				if (k_q == length_q) state_d = DONE;
+				else state_d = FETCH_I;
+			end
+			DONE: state_d = DONE;
+			default: state_d = INIT;
+		endcase
+	end: fsm_next_state_logic
+
+	always_ff @(posedge clk) begin: fsm_reg
+		if (~rst_n) begin
+			state_q <= INIT;
+			i_q <= '0;
+			j_q <= '0;
+			k_q <= 1'b1;
+			si_q <= '0;
+			sj_q <= '0;
+			length_q <= '0;
+		end else begin
+			state_q <= state_d;
+			i_q <= i_d;
+			j_q <= j_d;
+			k_q <= k_d;
+			si_q <= si_d;
+			sj_q <= sj_d;
+			length_q <= length_d;
+		end
+	end: fsm_reg
+
+endmodule: prga
diff --git a/src/pt_core_mem.v b/src/pt_core_mem.v
new file mode 100644
index 0000000..e11c523
--- /dev/null
+++ b/src/pt_core_mem.v
@@ -0,0 +1,66 @@
+module pt_core_mem (
+	address,
+	clock,
+	data,
+	wren,
+	q
+);
+
+	input [7:0] address;
+	input clock;
+	input [7:0] data;
+	input wren;
+	output [7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1 clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram altsyncram_component (
+		.address_a(address),
+		.clock0(clock),
+		.data_a(data),
+		.wren_a(wren),
+		.q_a(sub_wire0),
+		.aclr0(1'b0),
+		.aclr1(1'b0),
+		.address_b(1'b1),
+		.addressstall_a(1'b0),
+		.addressstall_b(1'b0),
+		.byteena_a(1'b1),
+		.byteena_b(1'b1),
+		.clock1(1'b1),
+		.clocken0(1'b1),
+		.clocken1(1'b1),
+		.clocken2(1'b1),
+		.clocken3(1'b1),
+		.data_b(1'b1),
+		.eccstatus(),
+		.q_b(),
+		.rden_a(1'b1),
+		.rden_b(1'b1),
+		.wren_b(1'b0)
+	);
+	defparam
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
diff --git a/src/pt_mem.qip b/src/pt_mem.qip
new file mode 100644
index 0000000..b9ac0e0
--- /dev/null
+++ b/src/pt_mem.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"

+set_global_assignment -name IP_TOOL_VERSION "24.1"

+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"

+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pt_mem.v"]

+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pt_mem_bb.v"]

diff --git a/src/pt_mem.v b/src/pt_mem.v
new file mode 100644
index 0000000..c50a8aa
--- /dev/null
+++ b/src/pt_mem.v
@@ -0,0 +1,175 @@
+// megafunction wizard: %RAM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: pt_mem.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2025  Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and any partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Altera and sold by Altera or its authorized distributors.  Please
+//refer to the Altera Software License Subscription Agreements
+//on the Quartus Prime software download page.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pt_mem (
+	address,
+	clock,
+	data,
+	wren,
+	q);
+
+	input	[7:0] address;
+	input	clock;
+	input	[7:0] data;
+	input	wren;
+	output	[7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PT",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+// Retrieval info: PRIVATE: JTAG_ID STRING "PT"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegData NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PT"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pt_mem_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/src/s_core_mem.v b/src/s_core_mem.v
new file mode 100644
index 0000000..f8f8abf
--- /dev/null
+++ b/src/s_core_mem.v
@@ -0,0 +1,66 @@
+module s_core_mem (
+	address,
+	clock,
+	data,
+	wren,
+	q
+);
+
+	input [7:0] address;
+	input clock;
+	input [7:0] data;
+	input wren;
+	output [7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1 clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram altsyncram_component (
+		.address_a(address),
+		.clock0(clock),
+		.data_a(data),
+		.wren_a(wren),
+		.q_a(sub_wire0),
+		.aclr0(1'b0),
+		.aclr1(1'b0),
+		.address_b(1'b1),
+		.addressstall_a(1'b0),
+		.addressstall_b(1'b0),
+		.byteena_a(1'b1),
+		.byteena_b(1'b1),
+		.clock1(1'b1),
+		.clocken0(1'b1),
+		.clocken1(1'b1),
+		.clocken2(1'b1),
+		.clocken3(1'b1),
+		.data_b(1'b1),
+		.eccstatus(),
+		.q_b(),
+		.rden_a(1'b1),
+		.rden_b(1'b1),
+		.wren_b(1'b0)
+	);
+	defparam
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
diff --git a/src/s_mem.qip b/src/s_mem.qip
new file mode 100644
index 0000000..ff1a06c
--- /dev/null
+++ b/src/s_mem.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "24.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "s_mem.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "s_mem_bb.v"]
diff --git a/src/s_mem.v b/src/s_mem.v
new file mode 100644
index 0000000..5fc1584
--- /dev/null
+++ b/src/s_mem.v
@@ -0,0 +1,174 @@
+// megafunction wizard: %RAM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: s_mem.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
+// ************************************************************
+
+//Copyright (C) 2025  Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and any partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Altera and sold by Altera or its authorized distributors.  Please
+//refer to the Altera Software License Subscription Agreements
+//on the Quartus Prime software download page.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module s_mem (
+	address,
+	clock,
+	data,
+	wren,
+	q);
+
+	input	[7:0] address;
+	input	clock;
+	input	[7:0] data;
+	input	wren;
+	output	[7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=S",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "SINGLE_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrData NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+// Retrieval info: PRIVATE: JTAG_ID STRING "S"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegData NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=S"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL s_mem_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf