| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2026-04-08 | Add screenshots | Warrick Lo | 4 | -0/+0 |
| 2026-04-08 | Add muli-core ARC4 cracking | Warrick Lo | 19 | -0/+2416 |
| 2026-04-08 | Add output file of 108 core cracking | Warrick Lo | 1 | -0/+0 |
| 2026-04-07 | add deadline | github-classroom[bot] | 1 | -0/+1 |
| 2026-03-17 | Initial commit | github-classroom[bot] | 6 | -0/+128 |
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index : rc4-decrypt | |
| A brute-force RC4 stream cipher decryption circuit in SystemVerilog. |
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