aboutsummaryrefslogtreecommitdiff
path: root/rtl/alu.sv
diff options
context:
space:
mode:
authorWarrick Lo <wlo@warricklo.net>2024-12-15 20:16:23 -0800
committerWarrick Lo <wlo@warricklo.net>2024-12-15 20:16:23 -0800
commitcf2e2cb508049d39458049a5028bbc26cbc9c34e (patch)
treebbd7993df5316c1cd74232f8519aaef8a9759ef9 /rtl/alu.sv
downloadrisc-processor-cf2e2cb508049d39458049a5028bbc26cbc9c34e.tar.xz
risc-processor-cf2e2cb508049d39458049a5028bbc26cbc9c34e.zip
Add RTL files
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'rtl/alu.sv')
-rw-r--r--rtl/alu.sv17
1 files changed, 17 insertions, 0 deletions
diff --git a/rtl/alu.sv b/rtl/alu.sv
new file mode 100644
index 0000000..c6d00bd
--- /dev/null
+++ b/rtl/alu.sv
@@ -0,0 +1,17 @@
+module ALU(Ain, Bin, op, out, status);
+ input [1:0] op;
+ input [15:0] Ain, Bin;
+ output [2:0] status;
+ output reg [15:0] out;
+
+ assign status[2] = out[15];
+ assign status[1] = (out[15] ^ Ain[15]) & ~(out[15] ^ Bin[15]);
+ assign status[0] = (out == 0);
+
+ always_comb case (op)
+ 2'b00: out = Ain + Bin;
+ 2'b01: out = Ain - Bin;
+ 2'b10: out = Ain & Bin;
+ 2'b11: out = ~Bin;
+ endcase
+endmodule: ALU