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| author | Warrick Lo <wlo@warricklo.net> | 2024-12-15 20:16:23 -0800 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2024-12-15 20:16:23 -0800 |
| commit | cf2e2cb508049d39458049a5028bbc26cbc9c34e (patch) | |
| tree | bbd7993df5316c1cd74232f8519aaef8a9759ef9 /rtl/shifter.sv | |
| download | risc-processor-cf2e2cb508049d39458049a5028bbc26cbc9c34e.tar.xz risc-processor-cf2e2cb508049d39458049a5028bbc26cbc9c34e.zip | |
Add RTL files
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'rtl/shifter.sv')
| -rw-r--r-- | rtl/shifter.sv | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/rtl/shifter.sv b/rtl/shifter.sv new file mode 100644 index 0000000..66e5c74 --- /dev/null +++ b/rtl/shifter.sv @@ -0,0 +1,12 @@ +module shifter(in, shift, sout); + input [1:0] shift; + input [15:0] in; + output reg [15:0] sout; + + always_comb case (shift) + 2'b00: sout = in; + 2'b01: sout = {in[14:0], 1'b0}; + 2'b10: sout = {1'b0, in[15:1]}; + 2'b11: sout = {in[15], in[15:1]}; + endcase +endmodule: shifter |