diff options
| -rw-r--r-- | mem/data.txt | 256 | ||||
| -rw-r--r-- | mem/data_cpu_tb.txt | 256 | ||||
| -rw-r--r-- | mem/data_lab8_check.txt | 256 | ||||
| -rw-r--r-- | mem/data_lab8_stage2.txt | 256 | ||||
| -rw-r--r-- | sim/wave.do | 66 | ||||
| -rw-r--r-- | tb/cpu_tb.sv | 39 | ||||
| -rw-r--r-- | tb/lab7_autograder_check.sv | 64 | ||||
| -rw-r--r-- | tb/lab7bonus_autograder_check.sv | 74 | ||||
| -rw-r--r-- | tb/lab7bonus_stage2_tb.sv | 47 |
9 files changed, 1314 insertions, 0 deletions
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0000000000000000 +@c3 0000000000000000 +@c4 0000000000000000 +@c5 0000000000000000 +@c6 0000000000000000 +@c7 0000000000000000 +@c8 0000000000000000 +@c9 0000000000000000 +@ca 0000000000000000 +@cb 0000000000000000 +@cc 0000000000000000 +@cd 0000000000000000 +@ce 0000000000000000 +@cf 0000000000000000 +@d0 0000000000000000 +@d1 0000000000000000 +@d2 0000000000000000 +@d3 0000000000000000 +@d4 0000000000000000 +@d5 0000000000000000 +@d6 0000000000000000 +@d7 0000000000000000 +@d8 0000000000000000 +@d9 0000000000000000 +@da 0000000000000000 +@db 0000000000000000 +@dc 0000000000000000 +@dd 0000000000000000 +@de 0000000000000000 +@df 0000000000000000 +@e0 0000000000000000 +@e1 0000000000000000 +@e2 0000000000000000 +@e3 0000000000000000 +@e4 0000000000000000 +@e5 0000000000000000 +@e6 0000000000000000 +@e7 0000000000000000 +@e8 0000000000000000 +@e9 0000000000000000 +@ea 0000000000000000 +@eb 0000000000000000 +@ec 0000000000000000 +@ed 0000000000000000 +@ee 0000000000000000 +@ef 0000000000000000 +@f0 0000000000000000 +@f1 0000000000000000 +@f2 0000000000000000 +@f3 0000000000000000 +@f4 0000000000000000 +@f5 0000000000000000 +@f6 0000000000000000 +@f7 0000000000000000 +@f8 0000000000000000 +@f9 0000000000000000 +@fa 0000000000000000 +@fb 0000000000000000 +@fc 0000000000000000 +@fd 0000000000000000 +@fe 0000000000000000 +@ff 0000000000000000 diff --git a/sim/wave.do b/sim/wave.do new file mode 100644 index 0000000..b5af4f9 --- /dev/null +++ b/sim/wave.do @@ -0,0 +1,66 @@ +radix define states { + "3'b000" "RESET", + "3'b001" "HALT", + "3'b010" "FETCH", + "3'b011" "DECODE", + "3'b100" "EXECUTE", + "3'b101" "MEMORY", + "3'b110" "WRITEBACK", + -default default +} +radix define memory { + "2'b00" "NOP", + "2'b01" "WRITE", + "2'b10" "READ", + -default default +} + +add wave -noupdate /lab7bonus_tb/err +add wave -noupdate /lab7bonus_tb/DUT/CPU/clk +add wave -noupdate /lab7bonus_tb/DUT/CPU/reset +add wave -noupdate /lab7bonus_tb/DUT/CPU/instruction +add wave -noupdate -radix hexadecimal /lab7bonus_tb/DUT/CPU/PC +add wave -noupdate -radix hexadecimal /lab7bonus_tb/DUT/CPU/pc_next +add wave -noupdate -radix states /lab7bonus_tb/DUT/CPU/FSM/state +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/opcode +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/op +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/sh +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/Rn +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/Rd +add wave -noupdate -expand -group {Instruction decoder} /lab7bonus_tb/DUT/CPU/Rm +add wave -noupdate -expand -group {Instruction decoder} -radix hexadecimal /lab7bonus_tb/DUT/CPU/sximm5 +add wave -noupdate -expand -group {Instruction decoder} -radix hexadecimal /lab7bonus_tb/DUT/CPU/sximm8 +add wave -noupdate -divider {PIPELINE REGISTERS} +add wave -noupdate -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/aout +add wave -noupdate -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/bout +add wave -noupdate -divider {CONTROL SIGNALS} +add wave -noupdate -expand -group {CPU Signals} /lab7bonus_tb/DUT/CPU/pc_reset +add wave -noupdate -expand -group {CPU Signals} /lab7bonus_tb/DUT/CPU/pc_load +add wave -noupdate -expand -group {CPU Signals} /lab7bonus_tb/DUT/CPU/ir_load +add wave -noupdate -expand -group {CPU Signals} /lab7bonus_tb/DUT/CPU/addr_sel +add wave -noupdate -expand -group {CPU Signals} -radix memory /lab7bonus_tb/DUT/CPU/mem_cmd +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/write +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/loada +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/loadb +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/loadc +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/loads +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/loadm +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/asel +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/bsel +add wave -noupdate -expand -group {Datapath Signals} /lab7bonus_tb/DUT/CPU/csel +add wave -noupdate -divider OUTPUT +add wave -noupdate -radix hexadecimal /lab7bonus_tb/DUT/CPU/mem_addr +add wave -noupdate /lab7bonus_tb/DUT/CPU/out +add wave -noupdate -expand -group Status /lab7bonus_tb/DUT/CPU/DP/N +add wave -noupdate -expand -group Status /lab7bonus_tb/DUT/CPU/DP/V +add wave -noupdate -expand -group Status /lab7bonus_tb/DUT/CPU/DP/Z +add wave -noupdate -divider REGISTERS/MEMORY +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R0 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R1 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R2 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R3 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R4 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R5 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R6 +add wave -noupdate -expand -group Registers -radix hexadecimal /lab7bonus_tb/DUT/CPU/DP/REGFILE/R7 +add wave -noupdate -radix decimal /lab7bonus_tb/DUT/MEM/mem diff --git a/tb/cpu_tb.sv b/tb/cpu_tb.sv new file mode 100644 index 0000000..deb5aad --- /dev/null +++ b/tb/cpu_tb.sv @@ -0,0 +1,39 @@ +`define M_NOP 2'b00 +`define M_READ 2'b10 +`define M_WRITE 2'b01 + +module cpu_tb; + reg err, clk, reset; + + tb_top DUT(clk, reset); + + always #5 clk = ~clk; + + initial begin + #2000; + $display("Time limit reached.\n"); + $stop; + end + + initial begin + clk = 1'b0; + reset = 1'b1; + #10; + reset = 1'b0; + end +endmodule: cpu_tb + +module tb_top(input clk, input reset); + wire write, N, V, Z; + wire [1:0] mem_cmd; + wire [8:0] mem_addr; + wire [15:0] din, dout, mem_data; + + ram #(16, 8, "data_cpu_tb.txt") MEM(clk, mem_addr[7:0], write, din, dout); + cpu CPU(clk, reset, mem_data, mem_cmd, mem_addr, din, N, V, Z); + + assign mem_data = (mem_cmd == `M_READ & ~mem_addr[8]) + ? dout : {16{1'bz}}; + assign din = {16{1'bz}}; + assign write = mem_cmd == `M_WRITE & ~mem_addr[8]; +endmodule: tb_top diff --git a/tb/lab7_autograder_check.sv b/tb/lab7_autograder_check.sv new file mode 100644 index 0000000..57a730e --- /dev/null +++ b/tb/lab7_autograder_check.sv @@ -0,0 +1,64 @@ +module lab7_check_tb; + reg err; + reg [3:0] KEY; + reg [9:0] SW; + wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; + wire [9:0] LEDR; + + lab7_top DUT(KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5); + + always #5 KEY[0] = ~KEY[0]; + + initial begin + #500; + $display("Time limit reached.\n"); + $stop; + end + + initial begin + err = 0; + KEY[0] = 1'b0; + KEY[1] = 1'b0; + + if (DUT.MEM.mem[0] !== 16'b1101000000000101) begin err = 1; $display("FAILED: mem[0] wrong; please set data.txt using Figure 6"); $stop; end + if (DUT.MEM.mem[1] !== 16'b0110000000100000) begin err = 1; $display("FAILED: mem[1] wrong; please set data.txt using Figure 6"); $stop; end + if (DUT.MEM.mem[2] !== 16'b1101001000000110) begin err = 1; $display("FAILED: mem[2] wrong; please set data.txt using Figure 6"); $stop; end + if (DUT.MEM.mem[3] !== 16'b1000001000100000) begin err = 1; $display("FAILED: mem[3] wrong; please set data.txt using Figure 6"); $stop; end + if (DUT.MEM.mem[4] !== 16'b1110000000000000) begin err = 1; $display("FAILED: mem[4] wrong; please set data.txt using Figure 6"); $stop; end + if (DUT.MEM.mem[5] !== 16'b1010101111001101) begin err = 1; $display("FAILED: mem[5] wrong; please set data.txt using Figure 6"); $stop; end + + @(negedge KEY[0]); + + KEY[1] = 1'b1; + + #10; + + if (DUT.CPU.PC !== 9'b0) begin err = 1; $display("FAILED: PC is not reset to zero."); $stop; end + + @(posedge DUT.CPU.PC or negedge DUT.CPU.PC); + + if (DUT.CPU.PC !== 9'h1) begin err = 1; $display("FAILED: PC should be 1."); $stop; end + + @(posedge DUT.CPU.PC or negedge DUT.CPU.PC); + + if (DUT.CPU.PC !== 9'h2) begin err = 1; $display("FAILED: PC should be 2."); $stop; end + if (DUT.CPU.DP.REGFILE.R0 !== 16'h5) begin err = 1; $display("FAILED: R0 should be 5."); $stop; end + + @(posedge DUT.CPU.PC or negedge DUT.CPU.PC); + + if (DUT.CPU.PC !== 9'h3) begin err = 1; $display("FAILED: PC should be 3."); $stop; end + if (DUT.CPU.DP.REGFILE.R1 !== 16'hABCD) begin err = 1; $display("FAILED: R1 should be 0xABCD. Looks like your LDR isn't working."); $stop; end + + @(posedge DUT.CPU.PC or negedge DUT.CPU.PC); + + if (DUT.CPU.PC !== 9'h4) begin err = 1; $display("FAILED: PC should be 4."); $stop; end + if (DUT.CPU.DP.REGFILE.R2 !== 16'h6) begin err = 1; $display("FAILED: R2 should be 6."); $stop; end + + @(posedge DUT.CPU.PC or negedge DUT.CPU.PC); + + if (DUT.CPU.PC !== 9'h5) begin err = 1; $display("FAILED: PC should be 5."); $stop; end + if (DUT.MEM.mem[6] !== 16'hABCD) begin err = 1; $display("FAILED: mem[6] wrong; looks like your STR isn't working"); $stop; end + + if (~err) $display("INTERFACE OK"); + end +endmodule: lab7_check_tb diff --git a/tb/lab7bonus_autograder_check.sv b/tb/lab7bonus_autograder_check.sv new file mode 100644 index 0000000..c772418 --- /dev/null +++ b/tb/lab7bonus_autograder_check.sv @@ -0,0 +1,74 @@ +module lab7bonus_check_tb; + reg [3:0] KEY; + reg [9:0] SW; + wire [9:0] LEDR; + wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; + reg err; + reg CLOCK_50; + + lab7bonus_top DUT(KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50); + + always #5 CLOCK_50 = ~CLOCK_50; + + initial begin + #2000; + $stop; + end + + initial begin + err = 0; + CLOCK_50 = 1'b0; + KEY[1] = 1'b0; // reset asserted + // check if program from Figure 2 in Lab 8 handout can be found loaded in memory + if (DUT.MEM.mem[0] !== 16'b1101000000001111) begin err = 1; $display("FAILED: mem[0] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[1] !== 16'b0110000000000000) begin err = 1; $display("FAILED: mem[1] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[2] !== 16'b1101000100000000) begin err = 1; $display("FAILED: mem[2] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[3] !== 16'b1101001000000000) begin err = 1; $display("FAILED: mem[3] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[4] !== 16'b1101001100010000) begin err = 1; $display("FAILED: mem[4] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[5] !== 16'b1101010000000001) begin err = 1; $display("FAILED: mem[5] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[6] !== 16'b1010001110100001) begin err = 1; $display("FAILED: mem[6] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[7] !== 16'b0110010110100000) begin err = 1; $display("FAILED: mem[7] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[8] !== 16'b1010001001000101) begin err = 1; $display("FAILED: mem[8] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[9] !== 16'b1010000100100100) begin err = 1; $display("FAILED: mem[9] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[10] !== 16'b1010100100000000) begin err = 1; $display("FAILED: mem[10] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[11] !== 16'b0010001111111010) begin err = 1; $display("FAILED: mem[11] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[12] !== 16'b1101001100010100) begin err = 1; $display("FAILED: mem[12] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[13] !== 16'b1000001101000000) begin err = 1; $display("FAILED: mem[13] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[14] !== 16'b1110000000000000) begin err = 1; $display("FAILED: mem[14] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[15] !== 16'b0000000000000100) begin err = 1; $display("FAILED: mem[15] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[16] !== 16'b0000000000110010) begin err = 1; $display("FAILED: mem[16] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[17] !== 16'b0000000011001000) begin err = 1; $display("FAILED: mem[17] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[18] !== 16'b0000000001100100) begin err = 1; $display("FAILED: mem[18] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[19] !== 16'b0000000111110100) begin err = 1; $display("FAILED: mem[19] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[20] !== 16'b1011101011011101) begin err = 1; $display("FAILED: mem[20] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + if (DUT.MEM.mem[21] !== 16'b0000000000000000) begin err = 1; $display("FAILED: mem[21] wrong; please set data.txt using lab7bonusfig2.s"); $stop; end + + #10; // wait until next falling edge of clock + KEY[1] = 1'b1; // reset de-asserted, PC still undefined if as in Figure 4 + + #10; // waiting for RST state to cause reset of PC + if (DUT.CPU.PC !== 9'h0) begin err = 1; $display("FAILED: PC did not reset to 0."); $stop; end + + // If your simlation never gets past the the line below, check if your CMP instruction is working + @(posedge LEDR[8]); // set LEDR[8] to one when executing HALT + + // NOTE: your program counter register output should be called PC and be inside a module with instance name CPU + // NOTE: if HALT is working, PC won't change after reaching 0xE + if (DUT.CPU.PC !== 9'hF) begin err = 1; $display("FAILED: PC at HALT is incorrect."); $stop; end + if (DUT.CPU.DP.REGFILE.R4 !== 16'h1) begin err = 1; $display("FAILED: R4 incorrect at exit; did MOV R4,#1 not work?"); $stop; end + if (DUT.CPU.DP.REGFILE.R0 !== 16'h4) begin err = 1; $display("FAILED: R0 incorrect at exit; did LDR R0,[R0] not work?"); $stop; end + + // check memory contents for result + if (DUT.MEM.mem[8'h14] === 16'h0) begin + err = 1; + $display("FAILED: mem[0x14] (result) is wrong;"); + if (DUT.CPU.DP.REGFILE.R3 === 16'h10) + $display(" hint: check if your BLT instruction skipped MOV R3, result"); + $stop; + end + if (DUT.MEM.mem[8'h14] !== 16'd850) begin err = 1; $display("FAILED: mem[0x14] (result) is wrong;"); $stop; end + + if (~err) $display("INTERFACE OK"); + $stop; + end +endmodule diff --git a/tb/lab7bonus_stage2_tb.sv b/tb/lab7bonus_stage2_tb.sv new file mode 100644 index 0000000..ca32dbd --- /dev/null +++ b/tb/lab7bonus_stage2_tb.sv @@ -0,0 +1,47 @@ +`define STATE_RESET 3'b000 +`define STATE_HALT 3'b001 +`define STATE_IF 3'b010 +`define STATE_DECODE 3'b011 +`define STATE_EXEC 3'b100 +`define STATE_MEM 3'b101 +`define STATE_WRITEBACK 3'b110 + +module lab7bonus_stage2_tb; + reg [3:0] KEY; + reg [9:0] SW; + wire [9:0] LEDR; + wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; + reg err; + reg CLOCK_50; + + lab7bonus_top DUT(KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50); + + always #5 CLOCK_50 = ~CLOCK_50; + + initial begin + #2000; + $stop; + end + + wire break = (LEDR[8] == 1'b1); + initial begin + err = 0; + CLOCK_50 = 1'b0; + KEY[1] = 1'b0; // reset asserted + #10; // wait until next falling edge of clock + KEY[1] = 1'b1; // reset de-asserted, PC still undefined if as in Figure 4 + while (~break) begin + // Change the following line to wait until your CPU starts to you fetch + // the next instruction (e.g., IF1 state from Lab 7 or equivalent in + // your design). DUT.CPU.FSM is not required for by the autograder + // for Lab 8. + @(posedge (DUT.CPU.FSM.state == `STATE_IF) or posedge break); + + @(negedge CLOCK_50); // show advance to negative edge of clock + $display("PC = %h", DUT.CPU.PC); + end + if (DUT.MEM.mem[25] !== -16'd23) begin err = 1; $display("FAILED: mem[25] wrong"); $stop; end + if (~err) $display("PASSED"); + $stop; + end +endmodule |