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| author | cristian-grecu <cristian.grecu@gmail.com> | 2026-01-15 13:31:15 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-01-15 13:31:15 -0800 |
| commit | 8d7122046785509970027c869ca580524ecefa83 (patch) | |
| tree | 56f0a8e7fccba9adb959b49bd740a8125caf92f7 | |
| parent | Update README.md (diff) | |
Update README.md
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -217,7 +217,7 @@ Before trying to finish the Verilog hardware, start by writing unit tests for al Be sure to exhaustively test **both** the SystemVerilog RTL code you write and the post-synthesis netlist Verilog file produced by Quartus (see the Tutorial). -The hardest part of this lab is getting the state machine right. We strongly urge you to draw (on paper) a bubble diagram showing the states, the transitions, and outputs of each transition. You are strongly urged to make sure you have your state machine bubble diagram done by Monday. If you are unclear how to do this, be sure to discuss with your TA during the lab period. When drawing your diagram for your state machine, make sure that you cover all of the possible input conditions. +The hardest part of this lab is getting the state machine right. We strongly urge you to draw (on paper) a bubble diagram showing the states, the transitions, and outputs of each transition. You are strongly urged to make sure you have your state machine bubble diagram done before writing the SystemVerilog code for it. If you are unclear how to do this, be sure to discuss with your TA during the lab period. When drawing your diagram for your state machine, make sure that you cover all of the possible input conditions. ### Post-synthesis simulation |