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| author | Warrick Lo <warrick.s.z.lo@gmail.com> | 2026-02-02 16:33:53 -0800 |
|---|---|---|
| committer | Warrick Lo <warrick.s.z.lo@gmail.com> | 2026-02-02 16:33:53 -0800 |
| commit | f3b2630ca2f6e00399c4d03acccc1e8a4c8d2c5c (patch) | |
| tree | 928b81379da21d704c1b31d8270f259001283cf0 /task1/card7seg.sv | |
| parent | add deadline (diff) | |
Add task 1 code
Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>
Diffstat (limited to 'task1/card7seg.sv')
| -rw-r--r-- | task1/card7seg.sv | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/task1/card7seg.sv b/task1/card7seg.sv index b994e3e..507c988 100644 --- a/task1/card7seg.sv +++ b/task1/card7seg.sv @@ -1,6 +1,23 @@ -module card7seg(input logic [3:0] SW, output logic [6:0] HEX0); - - // your code goes here - -endmodule +module card7seg(SW, HEX0); + input logic [3:0] SW; + output logic [6:0] HEX0; + always_comb begin + case (SW) + 1: HEX0 <= 7'b0001000; + 2: HEX0 <= 7'b0100100; + 3: HEX0 <= 7'b0110000; + 4: HEX0 <= 7'b0011001; + 5: HEX0 <= 7'b0010010; + 6: HEX0 <= 7'b0000010; + 7: HEX0 <= 7'b1111000; + 8: HEX0 <= 7'b0000000; + 9: HEX0 <= 7'b0010000; + 10: HEX0 <= 7'b1000000; + 11: HEX0 <= 7'b1100001; + 12: HEX0 <= 7'b0011000; + 13: HEX0 <= 7'b0001001; + default: HEX0 <= 7'b1111111; + endcase + end +endmodule: card7seg |