Add task 4 code

Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>

1 files changed, 20 insertions, 5 deletions

diff --git a/task4/card7seg.sv b/task4/card7seg.sv
index 6de0793..f683c89 100644
--- a/task4/card7seg.sv
+++ b/task4/card7seg.sv
@@ -1,6 +1,21 @@
-module card7seg(input logic [3:0] card, output logic [6:0] seg7);
-
-   // your code goes here
-
-endmodule
+module card7seg(in, hex);
+	input logic [3:0] in;
+	output logic [6:0] hex;
 
+	always_comb case (in)
+		1: hex <= 7'b0001000;
+		2: hex <= 7'b0100100;
+		3: hex <= 7'b0110000;
+		4: hex <= 7'b0011001;
+		5: hex <= 7'b0010010;
+		6: hex <= 7'b0000010;
+		7: hex <= 7'b1111000;
+		8: hex <= 7'b0000000;
+		9: hex <= 7'b0010000;
+		10: hex <= 7'b1000000;
+		11: hex <= 7'b1100001;
+		12: hex <= 7'b0011000;
+		13: hex <= 7'b0001001;
+		default: hex <= 7'b1111111;
+	endcase
+endmodule: card7seg