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| author | Warrick Lo <warrick.s.z.lo@gmail.com> | 2026-02-03 07:36:04 -0800 |
|---|---|---|
| committer | Warrick Lo <warrick.s.z.lo@gmail.com> | 2026-02-03 07:36:04 -0800 |
| commit | 7df28b9e812f278a93bdc68dea2c33850d2506af (patch) | |
| tree | 9c57f63d34154811b3c430c32d8170e3255b6752 /task5/datapath.sv | |
| parent | Add task 5 code, state machine broken in edge cases (diff) | |
Redesign state machine
Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>
Diffstat (limited to '')
| -rw-r--r-- | task5/datapath.sv | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/task5/datapath.sv b/task5/datapath.sv index 03f408d..ea99794 100644 --- a/task5/datapath.sv +++ b/task5/datapath.sv @@ -12,6 +12,8 @@ module datapath(slow_clock, fast_clock, resetb, logic [3:0] new_card, pcard1, pcard2, pcard3, dcard1, dcard2, dcard3; + assign pcard3_out = pcard3; + reg4 PCard1(new_card, load_pcard1, slow_clock, resetb, pcard1); reg4 PCard2(new_card, load_pcard2, slow_clock, resetb, pcard2); reg4 PCard3(new_card, load_pcard3, slow_clock, resetb, pcard3); |