Add task 5 code, state machine broken in edge cases

Signed-off-by: Warrick Lo <warrick.s.z.lo@gmail.com>

1 files changed, 24 insertions, 5 deletions

diff --git a/task5/scorehand.sv b/task5/scorehand.sv
index d6bd6cc..a472873 100644
--- a/task5/scorehand.sv
+++ b/task5/scorehand.sv
@@ -1,8 +1,27 @@
-module scorehand(input logic [3:0] card1, input logic [3:0] card2, input logic [3:0] card3, output logic [3:0] total);
+module scorehand(card1, card2, card3, total);
+	input logic [3:0] card1, card2, card3;
+	output logic [3:0] total;
 
-// The code describing scorehand will go here.  Remember this is a combinational
-// block. The function is described in the handout. Be sure to review Verilog
-// notes on bitwidth mismatches and signed/unsigned numbers.
+	logic [3:0] value1, value2, value3;
+	logic [4:0] sum;
 
-endmodule
+	always_comb begin
+		/* 10 and face cards have a value of zero. */
+		if (card1 >= 10) value1 = 0;
+		else value1 = card1;
+		if (card2 >= 10) value2 = 0;
+		else value2 = card2;
+		if (card3 >= 10) value3 = 0;
+		else value3 = card3;
 
+		/* Perform a modulo 10 operation on the total. */
+		sum = value1 + value2 + value3;
+		if (sum >= 20)
+			total = sum - 5'd20;
+		else if (sum >= 10)
+			total = sum - 5'd10;
+		else
+			total = sum;
+	end
+
+endmodule: scorehand