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Diffstat (limited to '')
| -rw-r--r-- | task1/card7seg.sv | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/task1/card7seg.sv b/task1/card7seg.sv index 507c988..ef9d5c7 100644 --- a/task1/card7seg.sv +++ b/task1/card7seg.sv @@ -2,22 +2,20 @@ module card7seg(SW, HEX0); input logic [3:0] SW; output logic [6:0] HEX0; - always_comb begin - case (SW) - 1: HEX0 <= 7'b0001000; - 2: HEX0 <= 7'b0100100; - 3: HEX0 <= 7'b0110000; - 4: HEX0 <= 7'b0011001; - 5: HEX0 <= 7'b0010010; - 6: HEX0 <= 7'b0000010; - 7: HEX0 <= 7'b1111000; - 8: HEX0 <= 7'b0000000; - 9: HEX0 <= 7'b0010000; - 10: HEX0 <= 7'b1000000; - 11: HEX0 <= 7'b1100001; - 12: HEX0 <= 7'b0011000; - 13: HEX0 <= 7'b0001001; - default: HEX0 <= 7'b1111111; - endcase - end + always_comb case (SW) + 1: HEX0 <= 7'b0001000; + 2: HEX0 <= 7'b0100100; + 3: HEX0 <= 7'b0110000; + 4: HEX0 <= 7'b0011001; + 5: HEX0 <= 7'b0010010; + 6: HEX0 <= 7'b0000010; + 7: HEX0 <= 7'b1111000; + 8: HEX0 <= 7'b0000000; + 9: HEX0 <= 7'b0010000; + 10: HEX0 <= 7'b1000000; + 11: HEX0 <= 7'b1100001; + 12: HEX0 <= 7'b0011000; + 13: HEX0 <= 7'b0001001; + default: HEX0 <= 7'b1111111; + endcase endmodule: card7seg |