diff options
Diffstat (limited to '')
| -rw-r--r-- | task1/card7seg.qws | bin | 0 -> 639 bytes | |||
| -rw-r--r-- | task1/card7seg.sv | 34 | ||||
| -rw-r--r-- | task1/tb_card7seg.sv | 113 |
3 files changed, 125 insertions, 22 deletions
diff --git a/task1/card7seg.qws b/task1/card7seg.qws Binary files differnew file mode 100644 index 0000000..689e37a --- /dev/null +++ b/task1/card7seg.qws diff --git a/task1/card7seg.sv b/task1/card7seg.sv index 507c988..ef9d5c7 100644 --- a/task1/card7seg.sv +++ b/task1/card7seg.sv @@ -2,22 +2,20 @@ module card7seg(SW, HEX0); input logic [3:0] SW; output logic [6:0] HEX0; - always_comb begin - case (SW) - 1: HEX0 <= 7'b0001000; - 2: HEX0 <= 7'b0100100; - 3: HEX0 <= 7'b0110000; - 4: HEX0 <= 7'b0011001; - 5: HEX0 <= 7'b0010010; - 6: HEX0 <= 7'b0000010; - 7: HEX0 <= 7'b1111000; - 8: HEX0 <= 7'b0000000; - 9: HEX0 <= 7'b0010000; - 10: HEX0 <= 7'b1000000; - 11: HEX0 <= 7'b1100001; - 12: HEX0 <= 7'b0011000; - 13: HEX0 <= 7'b0001001; - default: HEX0 <= 7'b1111111; - endcase - end + always_comb case (SW) + 1: HEX0 <= 7'b0001000; + 2: HEX0 <= 7'b0100100; + 3: HEX0 <= 7'b0110000; + 4: HEX0 <= 7'b0011001; + 5: HEX0 <= 7'b0010010; + 6: HEX0 <= 7'b0000010; + 7: HEX0 <= 7'b1111000; + 8: HEX0 <= 7'b0000000; + 9: HEX0 <= 7'b0010000; + 10: HEX0 <= 7'b1000000; + 11: HEX0 <= 7'b1100001; + 12: HEX0 <= 7'b0011000; + 13: HEX0 <= 7'b0001001; + default: HEX0 <= 7'b1111111; + endcase endmodule: card7seg diff --git a/task1/tb_card7seg.sv b/task1/tb_card7seg.sv index 3a985c9..5d68861 100644 --- a/task1/tb_card7seg.sv +++ b/task1/tb_card7seg.sv @@ -1,8 +1,113 @@ +`define ACE 7'b0001000 +`define TWO 7'b0100100 +`define THREE 7'b0110000 +`define FOUR 7'b0011001 +`define FIVE 7'b0010010 +`define SIX 7'b0000010 +`define SEVEN 7'b1111000 +`define EIGHT 7'b0000000 +`define NINE 7'b0010000 +`define TEN 7'b1000000 +`define JACK 7'b1100001 +`define QUEEN 7'b0011000 +`define KING 7'b0001001 +`define BLANK 7'b1111111 + module tb_card7seg(); + logic err; + logic [3:0] SW; + logic [6:0] HEX0; + + card7seg DUT(SW, HEX0); + + task check; + input logic [6:0] expected; + + if (HEX0 !== expected) begin + err = 1; + $display("FAILED: HEX is incorrect.",); + end + endtask: check + + + initial begin + err = 0; + + SW = 4'd0; + #5; + check(`BLANK); + #5; + + SW = 4'd1; + #5; + check(`ACE); + #5; + + SW = 4'd2; + #5; + check(`TWO); + #5; + + SW = 4'd3; + #5; + check(`THREE); + #5; + + SW = 4'd4; + #5; + check(`FOUR); + #5; + + SW = 4'd5; + #5; + check(`FIVE); + #5; + + SW = 4'd6; + #5; + check(`SIX); + #5; + + SW = 4'd7; + #5; + check(`SEVEN); + #5; + + SW = 4'd8; + #5; + check(`EIGHT); + #5; + + SW = 4'd9; + #5; + check(`NINE); + #5; + + SW = 4'd10; + #5; + check(`TEN); + #5; + + SW = 4'd11; + #5; + check(`JACK); + #5; + + SW = 4'd12; + #5; + check(`QUEEN); + #5; + + SW = 4'd13; + #5; + check(`KING); + #5; + + if (~err) + $display("All tests passed."); -// Your testbench goes here. Make sure your tests exercise the entire design -// in the .sv file. Note that in our tests the simulator will exit after -// 10,000 ticks (equivalent to "initial #10000 $finish();"). - + #10; + $stop; + end endmodule |