8 files changed, 150 insertions, 0 deletions
diff --git a/task4/.gitignore b/task4/.gitignore
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index 0000000..b0345dc
--- /dev/null
+++ b/task4/.gitignore
@@ -0,0 +1,18 @@
+.DS_Store
+transcript
+tcl_stacktrace.txt
+c5_pin_model_dump.txt
+*.mti
+*.mpf
+*.wlf
+*.qdb
+*.qpg
+*.qtl
+*.qpf
+*.sof
+*.bak
+work/
+db/
+incremental_db/
+simulation/
+output_files/
diff --git a/task4/card7seg.sv b/task4/card7seg.sv
new file mode 100644
index 0000000..6de0793
--- /dev/null
+++ b/task4/card7seg.sv
@@ -0,0 +1,6 @@
+module card7seg(input logic [3:0] card, output logic [6:0] seg7);
+
+   // your code goes here
+
+endmodule
+
diff --git a/task4/datapath.sv b/task4/datapath.sv
new file mode 100644
index 0000000..814ab3c
--- /dev/null
+++ b/task4/datapath.sv
@@ -0,0 +1,17 @@
+module datapath(input logic slow_clock, input logic fast_clock, input logic resetb,
+                input logic load_pcard1, input logic load_pcard2, input logic load_pcard3,
+                input logic load_dcard1, input logic load_dcard2, input logic load_dcard3,
+                output logic [3:0] pcard3_out,
+                output logic [3:0] pscore_out, output logic [3:0] dscore_out,
+                output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3,
+                output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0);
+
+// The code describing your datapath will go here.  Your datapath 
+// will hierarchically instantiate six card7seg blocks, two scorehand
+// blocks, and a dealcard block.  The registers may either be instatiated
+// or included as sequential always blocks directly in this file.
+//
+// Follow the block diagram in the Lab 1 handout closely as you write this code.
+
+endmodule
+
diff --git a/task4/dealcard.sv b/task4/dealcard.sv
new file mode 100644
index 0000000..cd1e781
--- /dev/null
+++ b/task4/dealcard.sv
@@ -0,0 +1,20 @@
+// Lucky you! We are giving you this code for free. There is nothing
+// here you need to add or write.
+
+module dealcard(input logic clock, input resetb, output logic [3:0] new_card);
+
+logic [3:0] dealer_card;
+
+always_ff @(posedge clock)
+  if (resetb == 0)
+     dealer_card <= 1;  
+  else
+     if (dealer_card == 13)
+	     dealer_card <= 1;
+	  else 
+	     dealer_card++;
+
+assign new_card = dealer_card;
+
+endmodule
+
diff --git a/task4/scorehand.sv b/task4/scorehand.sv
new file mode 100644
index 0000000..d6bd6cc
--- /dev/null
+++ b/task4/scorehand.sv
@@ -0,0 +1,8 @@
+module scorehand(input logic [3:0] card1, input logic [3:0] card2, input logic [3:0] card3, output logic [3:0] total);
+
+// The code describing scorehand will go here.  Remember this is a combinational
+// block. The function is described in the handout. Be sure to review Verilog
+// notes on bitwidth mismatches and signed/unsigned numbers.
+
+endmodule
+
diff --git a/task4/statemachine.sv b/task4/statemachine.sv
new file mode 100644
index 0000000..1a01db2
--- /dev/null
+++ b/task4/statemachine.sv
@@ -0,0 +1,13 @@
+module statemachine(input logic slow_clock, input logic resetb,
+                    input logic [3:0] dscore, input logic [3:0] pscore, input logic [3:0] pcard3,
+                    output logic load_pcard1, output logic load_pcard2, output logic load_pcard3,
+                    output logic load_dcard1, output logic load_dcard2, output logic load_dcard3,
+                    output logic player_win_light, output logic dealer_win_light);
+
+// The code describing your state machine will go here.  Remember that
+// a state machine consists of next state logic, output logic, and the 
+// registers that hold the state.  You will want to review your notes from
+// CPEN 211 or equivalent if you have forgotten how to write a state machine.
+
+endmodule
+
diff --git a/task4/task4.sv b/task4/task4.sv
new file mode 100644
index 0000000..1e2514f
--- /dev/null
+++ b/task4/task4.sv
@@ -0,0 +1,61 @@
+// This module contains a Verilog description of the top level module
+// Assuming you don't modify the inputs and outputs of the various submodules,
+// you should not have to modify anything in this file.
+
+module task4(input logic CLOCK_50, input logic [3:0] KEY, output logic [9:0] LEDR,
+            output logic [6:0] HEX5, output logic [6:0] HEX4, output logic [6:0] HEX3,
+            output logic [6:0] HEX2, output logic [6:0] HEX1, output logic [6:0] HEX0);
+
+// some local signals 
+
+logic fast_clock, slow_clock, resetb;
+logic load_pcard1, load_pcard2, load_pcard3;
+logic load_dcard1, load_dcard2, load_dcard3;
+logic [3:0] pscore, dscore;
+logic [3:0] pcard3;
+	
+assign resetb = KEY[3];
+assign slow_clock = KEY[0];
+assign fast_clock = CLOCK_50;
+
+// instantiate the datapath
+	
+datapath dp(.slow_clock(slow_clock),
+            .fast_clock(fast_clock),
+            .resetb(resetb),
+            .load_pcard1(load_pcard1),
+            .load_pcard2(load_pcard2),
+            .load_pcard3(load_pcard3),
+            .load_dcard1(load_dcard1),
+            .load_dcard2(load_dcard2),
+            .load_dcard3(load_dcard3),
+            .dscore_out(dscore),
+            .pscore_out(pscore),
+            .pcard3_out(pcard3),
+            .HEX5(HEX5),
+            .HEX4(HEX4),
+            .HEX3(HEX3),
+            .HEX2(HEX2),
+            .HEX1(HEX1),
+            .HEX0(HEX0));
+							
+assign LEDR[3:0] = pscore;
+assign LEDR[7:4] = dscore;
+
+// instantiate the state machine
+
+statemachine sm(.slow_clock(slow_clock),
+                .resetb(resetb),
+                .dscore(dscore),
+                .pscore(pscore),
+                .pcard3(pcard3),
+                .load_pcard1(load_pcard1),
+                .load_pcard2(load_pcard2),
+                .load_pcard3(load_pcard3),						  
+                .load_dcard1(load_dcard1),
+                .load_dcard2(load_dcard2),
+                .load_dcard3(load_dcard3),	
+                .player_win_light(LEDR[8]), 
+                .dealer_win_light(LEDR[9]));
+	
+endmodule
diff --git a/task4/tb_task4.sv b/task4/tb_task4.sv
new file mode 100644
index 0000000..0cc9c84
--- /dev/null
+++ b/task4/tb_task4.sv
@@ -0,0 +1,7 @@
+module tb_task4();
+
+// Your testbench goes here. Make sure your tests exercise the entire design
+// in the .sv file.  Note that in our tests the simulator will exit after
+// 100,000 ticks (equivalent to "initial #100000 $finish();").
+
+endmodule