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| author | github-classroom[bot] <66690702+github-classroom[bot]@users.noreply.github.com> | 2026-02-05 19:36:36 +0000 |
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| committer | GitHub <noreply@github.com> | 2026-02-05 19:36:36 +0000 |
| commit | ead28dd6fed440ccf4667c459778012bb0d95733 (patch) | |
| tree | bbc326fa1b487efc0fe163ef733a76c8a241fbb0 | |
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diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..13cb9d1 --- /dev/null +++ b/.gitignore @@ -0,0 +1,20 @@ +*.swp +.DS_Store +transcript +tcl_stacktrace.txt +c5_pin_model_dump.txt +*.mti +*.mpf +*.wlf +*.qdb +*.qpg +*.qtl +*.qws +*.qpf +*.sof +*.bak +work/ +db/ +incremental_db/ +simulation/ +output_files/ diff --git a/README.md b/README.md new file mode 100644 index 0000000..6eaa4aa --- /dev/null +++ b/README.md @@ -0,0 +1,394 @@ +# Lab 2: Circles and Triangles + +## Contents + +* [Overview](#overview) +* [External IP](#external-ip) + * [Task 1: Understanding the VGA adapter core](#task-1-understanding-the-vga-adapter-core) +* [Design](#design) + * [Task 2: Fill the Screen](#task-2-fill-the-screen) + * [Task 3: Bresenham Circle Algorithm](#task-3-bresenham-circle-algorithm) + * [Task 4: The Reuleaux Triangle](#task-4-the-reuleaux-triangle) +* [Deliverables and Evaluation](#deliverables-and-evaluation) + * [Marks Breakdown](#marks-breakdown) +* [Autograder Marking Process](#autograder-marking-process) + * [Autograder Marks](#autograder-marks) + + +## Overview + +In this lab, you will get more experience creating datapaths and state machines. You will also learn how to use an embedded VGA adapter core that we will give you to draw images on the screen. + +The top level diagram of your lab is shown below. The VGA Core is the part given to you, so all the excitement will be in the block labeled “your circuit.” + +<p align="center"><img src="figures/top_level.png" width="75%" height="75%" title="top-level design"></p> + +## External IP + +In the digital design industry, most designs incorporate modules provided by another team or another company. In this lab, we provide you with a VGA adapter core that converts a framebuffer view of the screen to the actual signals expected on the physical VGA port. + +### Task 1: Understanding the VGA adapter core + +The VGA adapter was created at the University of Toronto for a course similar to CPEN 311. The description below is enough for you to use the core, but you can find the complete specification at [the original site](http://www.eecg.utoronto.ca/~jayar/ece241_07F/vga). Some of the following figures have been taken with permission from that website (with permission). + +The VGA adapter has been set up to display a grid of 160×120 pixels, only _slightly_ worse than the [Atari 2600](https://en.wikipedia.org/wiki/Atari_2600_hardware). The interface is as shown below: + +<p align="center"><img src="figures/vga_adapter_ifc.jpg" width="50%" height="50%" title="VGA adapter interface (source: UofT)"></p> + +| Signal | Direction | Semantics | +| --- | --- | --- | +| resetn | input | active-low reset | +| clock | input | 50MHz clock | +| colour[2:0] | input | pixel colour (3 bits), each bit indicating the presence of one of the RGB components | +| x[7:0] | input | x coordinate of pixel to be drawn (0 ≤ x < 160) | +| y[6:0] | input | x coordinate of pixel to be drawn (0 ≤ x < 120) | +| plot | input | active-high plot enable signal | +| VGA_CLK | output | VGA clock (25 MHz) | +| VGA_R[9:0] | output | VGA red component | +| VGA_G[9:0] | output | VGA green component | +| VGA_B[9:0] | output | VGA blue component | +| VGA_HS | output | VGA horizontal sync | +| VGA_VS | output | VGA vertical sync | +| VGA_SYNC | output | VGA special synchronization mode | +| VGA_BLANK | output | VGA special blank mode | + +You will connect all outputs of the VGA core directly to the appropriate output pins of the FPGA. The VGA core will then continuously draw pixels on a VGA monitor connected to your board. + +You can picture the VGA pixel grid as shown below. The (_x_,_y_) position (0,0) is located on the top-left corner and (159,119) is at the other extreme end. The pixel colours are stored in each cell. This grid is stored in on-chip memory, and is called a framebuffer. + +<p align="center"><img src="figures/pixel_grid.png" width="60%" height="60%" title="screen coordinates (source: UofT)"></p> + +Initially, all pixels have a value that depends on how the FPGA was powered up (black if you're lucky) because the framebuffer is just a memory on the FPGA. To change the colour of a pixel, you must write to the framebuffer memory. To do this, you drive the _x_ input with the x position of the pixel, drive the _y_ input with the y position of the pixel, and _colour_ with the colour you wish to use. You then raise the _plot_ signal. At the next rising clock edge, the new colour is written to the framebuffer. At some point in the near future, during the next screen refresh cycle, the entire framebuffer is read out and all of the then-current pixel colours will be drawn on the screen. + +In the following timing diagram, two pixels are turned on: one at (15,62) and the other at (109,12). As you can see, the first pixel drawn is green and is placed at (15,62), while the second is a yellow pixel at (109,12). It is important to note that, at most, one pixel can be turned on each cycle — thus, if you want to turn on _m_ pixels, you need _m_ cycles. + +<p align="center"><img src="figures/interface_timing.png" width="80%" height="80%" title="VGA interface timing (source: UofT)"></p> + +The source code for the VGA adapter is in the `vga-core` folder in this repository. + +To help you understand the interface, we have created a `vga_demo.sv` file which connects the core I/O to switches on the DE1-SoC so you can experiment. We suggest you understand this module and try it out to make sure you understand how the inputs of the core work. (Note that you will not use this file for the other tasks in this Lab.) + +#### VGA bus widths on the DE1-SoC, DE10 Lite, and DE0-CV + +The VGA module we have provided has 10 bits of precision for the VGA red, green, and blue component signals. The DE1-SoC FPGA board we are using, though, has a DAC with only has 8 bits of precision for the same signals (you can see this in the pin assignment file). This means that you need to take the 8 most significant bits output by the VGA adapter core to drive the board outputs. (If you are using the DE0-CV or DE10 Lite, the DAC is even less accurate and only has 4 bits of precision for the three signals.) + +#### Simulation with the VGA core + +To simulate the VGA core in ModelSim, you will need to load the `altera_mf_ver` library to provide the block RAMs and PLL modules needed by the VGA core. For post-synthesis simulation, you will additionally require `cyclonev_ver`, `altera_ver`, and `altera_lnsim_ver` to model the FPGA logic cells, registers, and internal memories. + +We have also hacked up a simulation GUI similar to the one from Lab 1. It intercepts the signals passed to the VGA adapter and draws the pixels in an on-screen window. You need to load the `de1_vga_gui.tcl` script as you did for the GUI in Lab 1 (quo vide); the SystemVerilog component is included in the VGA adaptor Verilog (at the end of the file). If you wish, you can use this in conjunction with the fake DE1-SoC GUI from Lab 1, which might be helpful for Task 1; read Lab 1 for details. + +Note that your testbenches must not access any VGA adapter internals and must not depend on the GUI. + +#### Verification with the VGA core + +So how do you verify that things are working? + +Well, if you were really building a chip, you would verify the entire thing end-to-end by checking that the analog VGA outputs are exactly what they should be. But to save you some time (and learning the finer points of VGA signalling), we will not require you to test the VGA core itself — i.e., for this lab, it will suffice to test the inputs that go into the VGA core. + +This is easy to do with the RTL, since you can reach in and look at what is being fed to the VGA core. But what about the post-synthesis netlist? All those signals will have gone away, so you can't reach in and examine them using hierarchical naming. + +To help you with this, we have provided external ports for the VGA core inputs in the toplevel files. These ports will survive synthesis (and, indeed, be assigned pin locations on the FPGA), so you will be able to access them to validate your post-synthesis netlist. + + + +## Design + +### Task 2: Fill the Screen + +You will first create a simple circuit that fills the screen. Each column will be a different colour (repeating every 8 columns). Remember that you can only turn on one pixel at a time, so you would need an algorithm similar to this pseudocode: + + for x = 0 to 159: + for y = 0 to 119: + turn on pixel (x, y) with colour (x mod 8) + +You are to create a circuit that implements the above algorithm. A skeleton file `fillscreen.sv`, and a top-level skeleton `task2.sv`, are in the task2 folder. + +**As preparation of the midterm and exams, it is highly recommended that you +each work individually on this specific task. However, only one solution needs +to be pushed to GitHub.** + +The interface to the `fillscreen` module is as follows: + +| Signal | Direction | Semantics | +| --- | --- | --- | +| clk | input | clock | +| rst_n | input | active-low synchronous reset | +| colour | input | fill colour (ignored for Task 2) | +| start | input | assert to start filling the screen | +| done | output | goes high once the entire screen is filled | +| vga_* | output | outputs to the VGA adapter core | + +The user of the `fillscreen` module will assert `start` and hold it high until your module +asserts `done`. Any time after `done` is received, the user may de-assert +`start`. +After `start` is deasserted, your module should deassert `done` and must be +prepared for the possibility that `start` may be immediately asserted again. + +You will need to ignore the `colour` input for Task 2, but it will be useful for the later tasks. + +The `task2` module is the toplevel module you will load into the FPGA. It should instantiate the VGA adapter and your `fillscreen` module. +Upon asserting _reset_ (KEY3, active-low, synchronous) and with no other user activity, it should automatically start the process of filling the entire screen with black pixels. Due to the internal workings of the VGA adapter, clearing the screen can only be done by setting each pixel individually to a certain colour - we will use black (000) as the clear screen colour. After reset (which included clearing the VGA screen), the circuit waits for `start` to be asserted. Upon asserting `start`, the circuit proceeds to plot the vertical stripes as per the pseudocode above. At any point in time, if the `reset` signal is asserted, the circuit should initialize all the flip-flops in "your circuit" and clear the screen. Plotting the vertical stripes must be finished in 19,210 cycles of CLOCK_50 from the time the `start` input is _asserted_, i.e., one cycle per screen pixel plus 10 extra cycles; you will need to finish drawing and then assert `done` at some point within that time budget. + +Note that you are using CLOCK_50, the 50MHz clock, to clock your circuit. This is different than Lab 1 where you used a pushbutton switch for your clock. + +Exhaustively test your design by writing a testbench and simulating everything in ModelSim (hint: look at the counters first). You will need to demonstrate and submit comprehensive testbenches both for the fillscreen module and the toplevel module, with separate RTL and netlist testbenches. + +Make sure your pixel colours are correct. + + +### Task 3: Bresenham Circle Algorithm + +The Bresenham Circle algorithm is an integer-only circle-drawing algorithm. The basic algorithm is described in the following pseudocode (modified from Wikipedia): + + drawCircle(centre_x, centre_y, radius): + offset_y = 0 + offset_x = radius + crit = 1 - radius + while offset_y ≤ offset_x: + setPixel(centre_x + offset_x, centre_y + offset_y) -- octant 1 + setPixel(centre_x + offset_y, centre_y + offset_x) -- octant 2 + setPixel(centre_x - offset_x, centre_y + offset_y) -- octant 4 + setPixel(centre_x - offset_y, centre_y + offset_x) -- octant 3 + setPixel(centre_x - offset_x, centre_y - offset_y) -- octant 5 + setPixel(centre_x - offset_y, centre_y - offset_x) -- octant 6 + setPixel(centre_x + offset_x, centre_y - offset_y) -- octant 8 + setPixel(centre_x + offset_y, centre_y - offset_x) -- octant 7 + offset_y = offset_y + 1 + if crit ≤ 0: + crit = crit + 2 * offset_y + 1 + else: + offset_x = offset_x - 1 + crit = crit + 2 * (offset_y - offset_x) + 1 + +In this task, you are to implement a circuit that draws a circle with its centre at specified coordinates, a specified radius, and a specified colour. The interface to this `circle` module is as follows: + +| Signal | Direction | Semantics | +| --- | --- | --- | +| clk | input | clock | +| rst_n | input | active-low synchronous reset | +| colour | input | drawing colour | +| centre_x | input | the x-coordinate of the centre | +| centre_y | input | the y-coordinate of the centre | +| radius | input | the radius in pixels | +| start | input | assert to start filling the screen | +| done | output | goes high once the entire circle is drawn | +| vga_* | output | outputs to the VGA adapter core | + +As with the `fillscreen` module, the user will assert `start` and hold it high until your module asserts `done`. +After `start` is deasserted, your module should deassert `done` and must be +prepared for the possibility that `start` may be immediately asserted again. + +Your `circle` module must work for _any_ centre and radius inputs, _including_ centres and radii where parts of the circle would be off the screen (in which case you must draw only the on-screen parts). Any pixels whose coordinates fall outside of the screen area must not be drawn. It must only write pixels on the circle; it must not write other background pixels (i.e., do not fill the screen inside circle). + +The clock cycle budget you have for `circle` is the number of pixels that are actually drawn for the circle with the specified radius, plus 10 extra cycles. This budget includes pixels that _would have been_ drawn if the circle fit on the screen. You must assert `done` within the cycle budget to receive full credit. + +Upon `reset` (KEY3, active-low, synchronous) your circuit should initialize all flops/registers in "your circuit" and clear the VGA screen, identical to task 2. +Subsequently, upon `start` being asserted, +your top-level module `task3` should fill the screen with black pixels and draw +a pure-green circle with the centre at (80,60) and a radius of 40. The clock +cycle budget for this is 19,200 plus your `circle` budget plus 10. Note that +you must clear the screen to black even if on your board is initially black; +the initialization state of circuits cannot in general be relied upon. +You should test your `circle` module with different radii, not just what the +top-level module uses. + + +In designing the datapath for this algorithm, remember that you can only update +one pixel per clock cycle. This means that each iteration through the loop +should take at most 8 clock cycles to draw one pixel in each octant. + +As before, you will need to demonstrate and submit comprehensive testbenches both for the circle module and the toplevel module, separately for RTL and for the netlist. + +Be especially careful that your pixel positions are **exactly correct**. + +<!-- The autograder will treat the screen as initially undefined, and it will +compare the pixels you output against the reference solution, looking for +pixels that overlap, extra pixels, and missing pixels. If you draw a circle in +a different place than requested or with an incorrect radius, it is not likely +that many pixels will overlap. +--> + + + +### Task 4: The Reuleaux Triangle + +This task requires you to draw a [Reuleaux triangle](https://en.wikipedia.org/wiki/Reuleaux_triangle). This is a figure similar to a chubby equilateral triangle, where each triangle side is replaced by a section of a circle centred at the opposite corner: + +<p align="center"><img src="figures/reuleaux.svg" title="Reuleaux triangle"></p> + +You can think of this figure as the boundary of the intersection of three circles like this: + +<p align="center"><img src="figures/construction.svg" height="40%" width="40%" title="Construction by compass"></p> + +For the Reuleaux triangle, the _centre_ is defined as the point equidistant from all three corners, while the _diameter_ D is defined as usual as any segment that passes through the centre and whose endpoints lie on the Reuleaux triangle. Observe that this diameter is the same as the length of one side of the inscribed triangle, R1 + R2, and the same as the _radius_ of the three circles used to construct it. + +Your job is to write a module which draws this figure with the centre coordinates and the diameter as inputs (pointy end up, as in the figures above). You will probably want to use your circle design and carefully control when the pixels are drawn. + +Any fractional coordinates that you may need to compute must be converted to an +integer using fixed-point calculations. Because there are different ways to do +rounding, you will want to use these equations compute the location of the +three corners: + + assign c_x = centre_x; + assign c_y = centre_y; + assign c_x1 = c_x + diameter/2; + assign c_y1 = c_y + diameter * $sqrt(3)/6; + assign c_x2 = c_x - diameter/2; + assign c_y2 = c_y + diameter * $sqrt(3)/6; + assign c_x3 = c_x; + assign c_y3 = c_y - diameter * $sqrt(3)/3; + +Note that the code given above is not synthesizable. You will have to create a +synthesizable version that produces the exact same results as these equations +under simulation. + +Because of potential ambiguity in rounding, there may be pixel errors. To minimize these on our side, +we will only test your triangle with even diameters. To minimize these on your +side, be careful when clipping (i.e., omitting portions of the circle when +drawing). Clipping introduces up to four thresholds for the minimum or maximum +values of x and y. To reduce errors, choose as few thresholds as needed and reuse +the values already computed as shown above rather than trying to compute any other threshold values. + + +The interface for module `reuleaux` is the same as the one for `circle` from Task 3, except we specify the _diameter_ of the Reuleaux triangle instead of the radius of the circle. + +The clock cycle budget you have for `reuleaux` is the number of cycles that would be required to fully draw all three circles used to construct the Reuleaux triangle, plus 15 cycles; this includes pixels that fall outside of the screen coordinates. The `done` signal that indicates you are finished must be asserted within this budget. (Note that this is _a lot_ more than is needed to draw the actual triangle; you might want to think about how you would do it without wasting cycles on pixels you never draw.) + +Upon asserting `start` and with no other user activity, +your top-level module `task4` should fill the screen with black pixels and draw +a green Reuleaux triangle with the centre at (80,60) and a diameter of 80. The +cycle budget is 19,200 plus your `reuleaux` budget, plus 10 cycles. `Reset` must work identical to task 2 and 3. + + +As before, you will need to demonstrate and submit comprehensive testbenches both for the reuleaux module and the toplevel module, both for the RTL and the netlist. + +As with the circle task, be especially careful that your pixel positions are **exactly correct**. + +<!-- The autograder will compare pixel positions against a reference solution.--> + + + +## Deliverables and Evaluation + +Demo and grading process are described separately on Canvas. I will leave the previous +marking process below for you, so you know what you're missing. **Do** keep the +file names and structure as per the instructions in the "Old Marking Process" +shown below. + +In this lab (and future labs), you might need separate testbench files for RTL +(original source Verilog) and post-synthesis netlist (the `.vo` file generated +by Quartus). You will probably start the post-synthesis netlist testbench +(`tb_syn_*`) by copying a complete RTL testbench (`tb_rtl_*`), but often you need +to make changes to the netlist version, e.g. a different timespec, add extra tests, +change the clock period and other time delays, etc. + +### Marks Breakdown + +#### Task 1 + +No deliverables. + + +#### Task 2 [1 mark] + +Deliverables in folder `task2`: + +- Modified `task2.sv` (the toplevel) +- Modified `tb_rtl_task2.sv` +- Modified `tb_syn_task2.sv` +- Modified `fillscreen.sv` +- Modified `tb_rtl_fillscreen.sv` +- Modified `tb_syn_fillscreen.sv` +- Modified `README.md` describing the work done by each member of the team +- Any other modified/added source/testbench files for your design +- Do not copy the VGA files into the task files; this will conflict with the autograder's custom VGA module +- It is highly recommended that you each work individually on this specific task. However, only one solution needs to be pushed to GitHub. + +#### Task 3 [4 marks] + +Deliverables in folder `task3`: + +- Modified `task3.sv` (the toplevel) +- Modified `tb_syn_task3.sv` +- Modified `tb_rtl_task3.sv` +- Modified `circle.sv` +- Modified `tb_rtl_circle.sv` +- Modified `tb_syn_circle.sv` +- All `*.stats.rpt` files showing coverage results for all testbench files. +- Modified `README.md` describing the work done by each member of the team +- Any other modified/added source/testbench files for your design +- Do not copy the VGA files into the task files; this will conflict with the autograder's custom VGA module +- Use GitHub to track collaboration: each member must push their own changes, frequently + + +#### Task 4 [5 marks] + +Deliverables in folder `task4`: + +- Modified `task4.sv` (the toplevel) +- Modified `tb_rtl_task4.sv` +- Modified `tb_syn_task4.sv` +- Modified `reuleaux.sv` +- Modified `tb_rtl_reuleaux.sv` +- Modified `tb_syn_reuleaux.sv` +- All `*.stats.rpt` files showing coverage results for all testbench files. +- Modified `README.md` describing the work done by each member of the team +- Any other modified/added source/testbench files for your design +- Do not copy the VGA files into the task files; this will conflict with the autograder's custom VGA module +- Use GitHub to track collaboration: each member must push their own changes, frequently + + +## Autograder Marking Process + +The autograder will not be used for grading. This section is kept intact for +legacy purposes. + +In the past, the course placed a heavy emphasis on automated testing of labs. +This section is left here for legacy purposes. **In particular, you should +follow the rules below about not modifying filenames or module/port/signal +declarations that have been provided to you.** + +We will be marking your code via an automatic testing infrastructure. Your +autograder marks will depend on the fraction of the testcases your code passed +(i.e., which features work as specified), and how many cases your testbenches +cover. + +It is essential that you understand how this works so that you submit the +correct files — if our testsuite is unable to compile and test your code, you +will not receive marks. + +The testsuite evaluates each task separately. For each design task folder +(e.g., `task4`), it collects all Verilog files (`*.sv`) that do not begin with +`tb_` and compiles them **all together**. Separately, each required `tb_*.sv` +file is compiled with the relevant `*.sv` design files. This means that + +1. You must not **rename any files** we have provided. +1. You must not **add** any files that contain unused Verilog code; this may cause compilation to fail. +1. Your testbench files must begin with `tb_` and **correspond to design file names** (e.g., `tb_rtl_foo.sv` and `tb_syn_foo.sv` for design `foo.sv`). +1. You must not have **multiple copies of the same module** in separate committed source files in the same task folder. This will cause the compiler to fail because of duplicate module definitions. +1. Your modules must not **rely on files from another folder** with the exception of the VGA modules. The autograder will only look in the relevant task folder, and will have its own version of the VGA modules. +1. You must not copy the VGA files into the task folders; this will conflict with the autograder's custom VGA module. + +The autograder will instantiate and test each module exactly the way it is defined in the provided skeleton files. This means that +1. You must not **alter the module declarations, port lists, etc.**, in the provided skeleton files. +1. You must not **rename any modules, ports, or signals** in the provided skeleton files. +1. You must not **alter the width or polarity of any signal** in the skeleton files (e.g., everything depending on the clock is posedge-triggered, and `rst_n` must remain active-low). +1. Your sequential elements must be triggered **only on the positive edge of the clock** (and the negative edge of reset if you have an asynchronous active-low reset). No non-clock (or possibly reset) signal edges, no negative-edge clock signals, or other shenanigans. +1. You must not add logic to the clock and reset signals (e.g., invert them). When building digital hardware, it is extremely important that the clock and reset arrive at exactly the same time to all your FFs; otherwise your circuit will at best be slow and at worst not working. + +If your code does not compile, synthesize, and simulate under these conditions +(e.g., because of syntax errors, misconnected ports, or missing files), you +will receive **0 marks**. + +You will submit your RTL and you may optionally submit the post-synthesis +netlist `.vo` file (the autograder will generate its own netlist from your RTL +and mark that, though). + +### Autograder Marks (legacy, AG not used 2025w2) + +The evaluation of your submission consists of several parts: +- *30%*: automatic testing of your RTL code (`*.sv`) +- *20%*: automatic testing of your RTL testbench coverage (`tb_rtl_*.sv`) +- *30%*: automatic testing of the netlist we synthesize from your RTL +- *20%*: automatic testing of your post-synthesis testbench on the netlist we synthesize from your RTL (`tb_syn_*.sv`) diff --git a/bonus/ball.sv b/bonus/ball.sv new file mode 100644 index 0000000..0e4c9f3 --- /dev/null +++ b/bonus/ball.sv @@ -0,0 +1,11 @@ +module ball(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset + input logic [9:0] SW, output logic [9:0] LEDR, + output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, + output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK); + + // instantiate and connect the VGA adapter and your module + +endmodule: ball + diff --git a/bonus/balls.sv b/bonus/balls.sv new file mode 100644 index 0000000..06b72d7 --- /dev/null +++ b/bonus/balls.sv @@ -0,0 +1,11 @@ +module balls(input logic CLOCK_50, input logic [3:0] KEY, // KEY[3] is async active-low reset + input logic [9:0] SW, output logic [9:0] LEDR, + output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, + output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK); + + // instantiate and connect the VGA adapter and your module + +endmodule: balls + diff --git a/figures/construction.svg b/figures/construction.svg new file mode 100644 index 0000000..08d301e --- /dev/null +++ b/figures/construction.svg @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="utf-8"?> +<!-- Generator: Adobe Illustrator 22.0.1, SVG Export Plug-In . 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xmlns="http://www.w3.org/2000/svg" xmlns:xl="http://www.w3.org/1999/xlink" version="1.1" viewBox="36 40 107 106" width="107pt" height="106pt" xmlns:dc="http://purl.org/dc/elements/1.1/"> + <metadata> Produced by OmniGraffle 7.6 + <dc:date>2018-01-22 03:15:32 +0000</dc:date> + </metadata> + <defs/> + <g stroke="none" stroke-opacity="1" stroke-dasharray="none" fill="none" fill-opacity="1"> + <title>Canvas 1</title> + <g> + <title>Layer 1</title> + <path d="M 141.34092 131.15601 C 141.34044 92.86243 120.53398 59.43051 89.61096 41.542 C 58.68794 59.430986 37.88148 92.86243 37.881 131.15601 C 53.09871 139.9592 70.76545 145 89.61096 145 C 108.45647 145 126.12321 139.9592 141.34092 131.15601 Z" stroke="#011893" stroke-linecap="butt" stroke-linejoin="round" stroke-width="2"/> + </g> + </g> +</svg> diff --git a/figures/top_level.png b/figures/top_level.png Binary files differnew file mode 100644 index 0000000..0dc05c9 --- /dev/null +++ b/figures/top_level.png diff --git a/figures/top_level.png.png b/figures/top_level.png.png Binary files differnew file mode 100644 index 0000000..0dc05c9 --- /dev/null +++ b/figures/top_level.png.png diff --git a/figures/toplevel.png b/figures/toplevel.png Binary files differnew file mode 100644 index 0000000..9b18d58 --- /dev/null +++ b/figures/toplevel.png diff --git a/figures/vga_adapter_ifc.jpg b/figures/vga_adapter_ifc.jpg Binary files differnew file mode 100644 index 0000000..b2b1a6d --- /dev/null +++ b/figures/vga_adapter_ifc.jpg diff --git a/settings/DE0_CV.qsf b/settings/DE0_CV.qsf new file mode 100644 index 0000000..b2e6f0e --- /dev/null +++ b/settings/DE0_CV.qsf @@ -0,0 +1,515 @@ +#============================================================
+# Altera DE0-CV board settings
+#============================================================
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CEBA4F23C7
+set_global_assignment -name TOP_LEVEL_ENTITY "DE0_CV"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_M9 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# CLOCK2
+#============================================================
+set_location_assignment PIN_H13 -to CLOCK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
+
+#============================================================
+# CLOCK3
+#============================================================
+set_location_assignment PIN_E10 -to CLOCK3_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+#============================================================
+# CLOCK4
+#============================================================
+set_location_assignment PIN_V15 -to CLOCK4_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50
+
+#============================================================
+# DRAM
+#============================================================
+set_location_assignment PIN_W8 -to DRAM_ADDR[0]
+set_location_assignment PIN_T8 -to DRAM_ADDR[1]
+set_location_assignment PIN_U11 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y10 -to DRAM_ADDR[3]
+set_location_assignment PIN_N6 -to DRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to DRAM_ADDR[5]
+set_location_assignment PIN_P12 -to DRAM_ADDR[6]
+set_location_assignment PIN_P7 -to DRAM_ADDR[7]
+set_location_assignment PIN_P8 -to DRAM_ADDR[8]
+set_location_assignment PIN_R5 -to DRAM_ADDR[9]
+set_location_assignment PIN_U8 -to DRAM_ADDR[10]
+set_location_assignment PIN_P6 -to DRAM_ADDR[11]
+set_location_assignment PIN_R7 -to DRAM_ADDR[12]
+set_location_assignment PIN_T7 -to DRAM_BA[0]
+set_location_assignment PIN_AB7 -to DRAM_BA[1]
+set_location_assignment PIN_V6 -to DRAM_CAS_N
+set_location_assignment PIN_R6 -to DRAM_CKE
+set_location_assignment PIN_AB11 -to DRAM_CLK
+set_location_assignment PIN_U6 -to DRAM_CS_N
+set_location_assignment PIN_Y9 -to DRAM_DQ[0]
+set_location_assignment PIN_T10 -to DRAM_DQ[1]
+set_location_assignment PIN_R9 -to DRAM_DQ[2]
+set_location_assignment PIN_Y11 -to DRAM_DQ[3]
+set_location_assignment PIN_R10 -to DRAM_DQ[4]
+set_location_assignment PIN_R11 -to DRAM_DQ[5]
+set_location_assignment PIN_R12 -to DRAM_DQ[6]
+set_location_assignment PIN_AA12 -to DRAM_DQ[7]
+set_location_assignment PIN_AA9 -to DRAM_DQ[8]
+set_location_assignment PIN_AB8 -to DRAM_DQ[9]
+set_location_assignment PIN_AA8 -to DRAM_DQ[10]
+set_location_assignment PIN_AA7 -to DRAM_DQ[11]
+set_location_assignment PIN_V10 -to DRAM_DQ[12]
+set_location_assignment PIN_V9 -to DRAM_DQ[13]
+set_location_assignment PIN_U10 -to DRAM_DQ[14]
+set_location_assignment PIN_T9 -to DRAM_DQ[15]
+set_location_assignment PIN_U12 -to DRAM_LDQM
+set_location_assignment PIN_AB6 -to DRAM_RAS_N
+set_location_assignment PIN_N8 -to DRAM_UDQM
+set_location_assignment PIN_AB5 -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+
+#============================================================
+# GPIO
+#============================================================
+set_location_assignment PIN_N16 -to GPIO_0[0]
+set_location_assignment PIN_B16 -to GPIO_0[1]
+set_location_assignment PIN_M16 -to GPIO_0[2]
+set_location_assignment PIN_C16 -to GPIO_0[3]
+set_location_assignment PIN_D17 -to GPIO_0[4]
+set_location_assignment PIN_K20 -to GPIO_0[5]
+set_location_assignment PIN_K21 -to GPIO_0[6]
+set_location_assignment PIN_K22 -to GPIO_0[7]
+set_location_assignment PIN_M20 -to GPIO_0[8]
+set_location_assignment PIN_M21 -to GPIO_0[9]
+set_location_assignment PIN_N21 -to GPIO_0[10]
+set_location_assignment PIN_R22 -to GPIO_0[11]
+set_location_assignment PIN_R21 -to GPIO_0[12]
+set_location_assignment PIN_T22 -to GPIO_0[13]
+set_location_assignment PIN_N20 -to GPIO_0[14]
+set_location_assignment PIN_N19 -to GPIO_0[15]
+set_location_assignment PIN_M22 -to GPIO_0[16]
+set_location_assignment PIN_P19 -to GPIO_0[17]
+set_location_assignment PIN_L22 -to GPIO_0[18]
+set_location_assignment PIN_P17 -to GPIO_0[19]
+set_location_assignment PIN_P16 -to GPIO_0[20]
+set_location_assignment PIN_M18 -to GPIO_0[21]
+set_location_assignment PIN_L18 -to GPIO_0[22]
+set_location_assignment PIN_L17 -to GPIO_0[23]
+set_location_assignment PIN_L19 -to GPIO_0[24]
+set_location_assignment PIN_K17 -to GPIO_0[25]
+set_location_assignment PIN_K19 -to GPIO_0[26]
+set_location_assignment PIN_P18 -to GPIO_0[27]
+set_location_assignment PIN_R15 -to GPIO_0[28]
+set_location_assignment PIN_R17 -to GPIO_0[29]
+set_location_assignment PIN_R16 -to GPIO_0[30]
+set_location_assignment PIN_T20 -to GPIO_0[31]
+set_location_assignment PIN_T19 -to GPIO_0[32]
+set_location_assignment PIN_T18 -to GPIO_0[33]
+set_location_assignment PIN_T17 -to GPIO_0[34]
+set_location_assignment PIN_T15 -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+
+set_location_assignment PIN_H16 -to GPIO_1[0]
+set_location_assignment PIN_A12 -to GPIO_1[1]
+set_location_assignment PIN_H15 -to GPIO_1[2]
+set_location_assignment PIN_B12 -to GPIO_1[3]
+set_location_assignment PIN_A13 -to GPIO_1[4]
+set_location_assignment PIN_B13 -to GPIO_1[5]
+set_location_assignment PIN_C13 -to GPIO_1[6]
+set_location_assignment PIN_D13 -to GPIO_1[7]
+set_location_assignment PIN_G18 -to GPIO_1[8]
+set_location_assignment PIN_G17 -to GPIO_1[9]
+set_location_assignment PIN_H18 -to GPIO_1[10]
+set_location_assignment PIN_J18 -to GPIO_1[11]
+set_location_assignment PIN_J19 -to GPIO_1[12]
+set_location_assignment PIN_G11 -to GPIO_1[13]
+set_location_assignment PIN_H10 -to GPIO_1[14]
+set_location_assignment PIN_J11 -to GPIO_1[15]
+set_location_assignment PIN_H14 -to GPIO_1[16]
+set_location_assignment PIN_A15 -to GPIO_1[17]
+set_location_assignment PIN_J13 -to GPIO_1[18]
+set_location_assignment PIN_L8 -to GPIO_1[19]
+set_location_assignment PIN_A14 -to GPIO_1[20]
+set_location_assignment PIN_B15 -to GPIO_1[21]
+set_location_assignment PIN_C15 -to GPIO_1[22]
+set_location_assignment PIN_E14 -to GPIO_1[23]
+set_location_assignment PIN_E15 -to GPIO_1[24]
+set_location_assignment PIN_E16 -to GPIO_1[25]
+set_location_assignment PIN_F14 -to GPIO_1[26]
+set_location_assignment PIN_F15 -to GPIO_1[27]
+set_location_assignment PIN_F13 -to GPIO_1[28]
+set_location_assignment PIN_F12 -to GPIO_1[29]
+set_location_assignment PIN_G16 -to GPIO_1[30]
+set_location_assignment PIN_G15 -to GPIO_1[31]
+set_location_assignment PIN_G13 -to GPIO_1[32]
+set_location_assignment PIN_G12 -to GPIO_1[33]
+set_location_assignment PIN_J17 -to GPIO_1[34]
+set_location_assignment PIN_K16 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_U21 -to HEX0[0]
+set_location_assignment PIN_V21 -to HEX0[1]
+set_location_assignment PIN_W22 -to HEX0[2]
+set_location_assignment PIN_W21 -to HEX0[3]
+set_location_assignment PIN_Y22 -to HEX0[4]
+set_location_assignment PIN_Y21 -to HEX0[5]
+set_location_assignment PIN_AA22 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AA20 -to HEX1[0]
+set_location_assignment PIN_AB20 -to HEX1[1]
+set_location_assignment PIN_AA19 -to HEX1[2]
+set_location_assignment PIN_AA18 -to HEX1[3]
+set_location_assignment PIN_AB18 -to HEX1[4]
+set_location_assignment PIN_AA17 -to HEX1[5]
+set_location_assignment PIN_U22 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_Y19 -to HEX2[0]
+set_location_assignment PIN_AB17 -to HEX2[1]
+set_location_assignment PIN_AA10 -to HEX2[2]
+set_location_assignment PIN_Y14 -to HEX2[3]
+set_location_assignment PIN_V14 -to HEX2[4]
+set_location_assignment PIN_AB22 -to HEX2[5]
+set_location_assignment PIN_AB21 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_Y16 -to HEX3[0]
+set_location_assignment PIN_W16 -to HEX3[1]
+set_location_assignment PIN_Y17 -to HEX3[2]
+set_location_assignment PIN_V16 -to HEX3[3]
+set_location_assignment PIN_U17 -to HEX3[4]
+set_location_assignment PIN_V18 -to HEX3[5]
+set_location_assignment PIN_V19 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_U20 -to HEX4[0]
+set_location_assignment PIN_Y20 -to HEX4[1]
+set_location_assignment PIN_V20 -to HEX4[2]
+set_location_assignment PIN_U16 -to HEX4[3]
+set_location_assignment PIN_U15 -to HEX4[4]
+set_location_assignment PIN_Y15 -to HEX4[5]
+set_location_assignment PIN_P9 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_N9 -to HEX5[0]
+set_location_assignment PIN_M8 -to HEX5[1]
+set_location_assignment PIN_T14 -to HEX5[2]
+set_location_assignment PIN_P14 -to HEX5[3]
+set_location_assignment PIN_C1 -to HEX5[4]
+set_location_assignment PIN_C2 -to HEX5[5]
+set_location_assignment PIN_W19 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_U7 -to KEY[0]
+set_location_assignment PIN_W9 -to KEY[1]
+set_location_assignment PIN_M7 -to KEY[2]
+set_location_assignment PIN_M6 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# KEY (Reset)
+#============================================================
+set_location_assignment PIN_P22 -to FPGA_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_RESET_N
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_AA2 -to LEDR[0]
+set_location_assignment PIN_AA1 -to LEDR[1]
+set_location_assignment PIN_W2 -to LEDR[2]
+set_location_assignment PIN_Y3 -to LEDR[3]
+set_location_assignment PIN_N2 -to LEDR[4]
+set_location_assignment PIN_N1 -to LEDR[5]
+set_location_assignment PIN_U2 -to LEDR[6]
+set_location_assignment PIN_U1 -to LEDR[7]
+set_location_assignment PIN_L2 -to LEDR[8]
+set_location_assignment PIN_L1 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# microSD Card
+#============================================================
+set_location_assignment PIN_H11 -to SD_CLK
+set_location_assignment PIN_B11 -to SD_CMD
+set_location_assignment PIN_K9 -to SD_DATA[0]
+set_location_assignment PIN_D12 -to SD_DATA[1]
+set_location_assignment PIN_E12 -to SD_DATA[2]
+set_location_assignment PIN_C11 -to SD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DATA[3]
+
+#============================================================
+# PS2
+#============================================================
+set_location_assignment PIN_D3 -to PS2_CLK
+set_location_assignment PIN_G2 -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+
+set_location_assignment PIN_E2 -to PS2_CLK2
+set_location_assignment PIN_G1 -to PS2_DAT2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_U13 -to SW[0]
+set_location_assignment PIN_V13 -to SW[1]
+set_location_assignment PIN_T13 -to SW[2]
+set_location_assignment PIN_T12 -to SW[3]
+set_location_assignment PIN_AA15 -to SW[4]
+set_location_assignment PIN_AB15 -to SW[5]
+set_location_assignment PIN_AA14 -to SW[6]
+set_location_assignment PIN_AA13 -to SW[7]
+set_location_assignment PIN_AB13 -to SW[8]
+set_location_assignment PIN_AB12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_B6 -to VGA_B[0]
+set_location_assignment PIN_B7 -to VGA_B[1]
+set_location_assignment PIN_A8 -to VGA_B[2]
+set_location_assignment PIN_A7 -to VGA_B[3]
+set_location_assignment PIN_L7 -to VGA_G[0]
+set_location_assignment PIN_K7 -to VGA_G[1]
+set_location_assignment PIN_J7 -to VGA_G[2]
+set_location_assignment PIN_J8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_R[0]
+set_location_assignment PIN_B10 -to VGA_R[1]
+set_location_assignment PIN_C9 -to VGA_R[2]
+set_location_assignment PIN_A5 -to VGA_R[3]
+set_location_assignment PIN_H8 -to VGA_HS
+set_location_assignment PIN_G8 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+
+
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SDC_FILE DE0_CV.sdc
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to VGA_*
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/settings/DE10_Lite.qsf b/settings/DE10_Lite.qsf new file mode 100644 index 0000000..35833b9 --- /dev/null +++ b/settings/DE10_Lite.qsf @@ -0,0 +1,446 @@ +#============================================================ +# Altera DE10-Lite board settings +#============================================================ + + +set_global_assignment -name FAMILY "MAX 10 FPGA" +set_global_assignment -name DEVICE 10M50DAF484C6GES +set_global_assignment -name TOP_LEVEL_ENTITY "DE10_Lite" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name SDC_FILE DE10_Lite.sdc +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_ADC_10 +set_location_assignment PIN_P11 -to CLOCK_50 +set_location_assignment PIN_N14 -to CLOCK2_50 +set_location_assignment PIN_N5 -to CLOCK_ADC_10 + +#============================================================ +# Arduino +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N + +#============================================================ +# Accelerometer +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_SDO +set_location_assignment PIN_AB16 -to G_SENSOR_CS_N +set_location_assignment PIN_Y14 -to G_SENSOR_INT[1] +set_location_assignment PIN_Y13 -to G_SENSOR_INT[2] +set_location_assignment PIN_AB15 -to G_SENSOR_SCLK +set_location_assignment PIN_V11 -to G_SENSOR_SDI +set_location_assignment PIN_V12 -to G_SENSOR_SDO + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +#============================================================ +# HEX0 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# HEX2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] + +#============================================================ +# HEX3 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] + +#============================================================ +# HEX4 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] + +#============================================================ +# HEX5 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS + +#============================================================ +# End of pin and io_standard assignments +#============================================================ + diff --git a/settings/DE1_SoC.qsf b/settings/DE1_SoC.qsf new file mode 100644 index 0000000..f20aaec --- /dev/null +++ b/settings/DE1_SoC.qsf @@ -0,0 +1,953 @@ +#============================================================
+# Altera DE1-SoC board settings
+#============================================================
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SDC_FILE DE1_SoC.sdc
+
+
+#============================================================
+# ADC
+#============================================================
+set_location_assignment PIN_AJ4 -to ADC_CS_N
+set_location_assignment PIN_AK4 -to ADC_DIN
+set_location_assignment PIN_AK3 -to ADC_DOUT
+set_location_assignment PIN_AK2 -to ADC_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
+
+#============================================================
+# AUD
+#============================================================
+set_location_assignment PIN_K7 -to AUD_ADCDAT
+set_location_assignment PIN_K8 -to AUD_ADCLRCK
+set_location_assignment PIN_H7 -to AUD_BCLK
+set_location_assignment PIN_J7 -to AUD_DACDAT
+set_location_assignment PIN_H8 -to AUD_DACLRCK
+set_location_assignment PIN_G7 -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# CLOCK2
+#============================================================
+set_location_assignment PIN_AA16 -to CLOCK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
+
+#============================================================
+# CLOCK3
+#============================================================
+set_location_assignment PIN_Y26 -to CLOCK3_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+
+#============================================================
+# CLOCK4
+#============================================================
+set_location_assignment PIN_K14 -to CLOCK4_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50
+
+#============================================================
+# DRAM
+#============================================================
+set_location_assignment PIN_AK14 -to DRAM_ADDR[0]
+set_location_assignment PIN_AH14 -to DRAM_ADDR[1]
+set_location_assignment PIN_AG15 -to DRAM_ADDR[2]
+set_location_assignment PIN_AE14 -to DRAM_ADDR[3]
+set_location_assignment PIN_AB15 -to DRAM_ADDR[4]
+set_location_assignment PIN_AC14 -to DRAM_ADDR[5]
+set_location_assignment PIN_AD14 -to DRAM_ADDR[6]
+set_location_assignment PIN_AF15 -to DRAM_ADDR[7]
+set_location_assignment PIN_AH15 -to DRAM_ADDR[8]
+set_location_assignment PIN_AG13 -to DRAM_ADDR[9]
+set_location_assignment PIN_AG12 -to DRAM_ADDR[10]
+set_location_assignment PIN_AH13 -to DRAM_ADDR[11]
+set_location_assignment PIN_AJ14 -to DRAM_ADDR[12]
+set_location_assignment PIN_AF13 -to DRAM_BA[0]
+set_location_assignment PIN_AJ12 -to DRAM_BA[1]
+set_location_assignment PIN_AF11 -to DRAM_CAS_N
+set_location_assignment PIN_AK13 -to DRAM_CKE
+set_location_assignment PIN_AH12 -to DRAM_CLK
+set_location_assignment PIN_AG11 -to DRAM_CS_N
+set_location_assignment PIN_AK6 -to DRAM_DQ[0]
+set_location_assignment PIN_AJ7 -to DRAM_DQ[1]
+set_location_assignment PIN_AK7 -to DRAM_DQ[2]
+set_location_assignment PIN_AK8 -to DRAM_DQ[3]
+set_location_assignment PIN_AK9 -to DRAM_DQ[4]
+set_location_assignment PIN_AG10 -to DRAM_DQ[5]
+set_location_assignment PIN_AK11 -to DRAM_DQ[6]
+set_location_assignment PIN_AJ11 -to DRAM_DQ[7]
+set_location_assignment PIN_AH10 -to DRAM_DQ[8]
+set_location_assignment PIN_AJ10 -to DRAM_DQ[9]
+set_location_assignment PIN_AJ9 -to DRAM_DQ[10]
+set_location_assignment PIN_AH9 -to DRAM_DQ[11]
+set_location_assignment PIN_AH8 -to DRAM_DQ[12]
+set_location_assignment PIN_AH7 -to DRAM_DQ[13]
+set_location_assignment PIN_AJ6 -to DRAM_DQ[14]
+set_location_assignment PIN_AJ5 -to DRAM_DQ[15]
+set_location_assignment PIN_AB13 -to DRAM_LDQM
+set_location_assignment PIN_AE13 -to DRAM_RAS_N
+set_location_assignment PIN_AK12 -to DRAM_UDQM
+set_location_assignment PIN_AA13 -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+
+#============================================================
+# FAN
+#============================================================
+set_location_assignment PIN_AA12 -to FAN_CTRL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL
+
+#============================================================
+# FPGA
+#============================================================
+set_location_assignment PIN_J12 -to FPGA_I2C_SCLK
+set_location_assignment PIN_K12 -to FPGA_I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT
+
+#============================================================
+# GPIO
+#============================================================
+set_location_assignment PIN_AC18 -to GPIO_0[0]
+set_location_assignment PIN_AH18 -to GPIO_0[10]
+set_location_assignment PIN_AH17 -to GPIO_0[11]
+set_location_assignment PIN_AG16 -to GPIO_0[12]
+set_location_assignment PIN_AE16 -to GPIO_0[13]
+set_location_assignment PIN_AF16 -to GPIO_0[14]
+set_location_assignment PIN_AG17 -to GPIO_0[15]
+set_location_assignment PIN_AA18 -to GPIO_0[16]
+set_location_assignment PIN_AA19 -to GPIO_0[17]
+set_location_assignment PIN_AE17 -to GPIO_0[18]
+set_location_assignment PIN_AC20 -to GPIO_0[19]
+set_location_assignment PIN_Y17 -to GPIO_0[1]
+set_location_assignment PIN_AH19 -to GPIO_0[20]
+set_location_assignment PIN_AJ20 -to GPIO_0[21]
+set_location_assignment PIN_AH20 -to GPIO_0[22]
+set_location_assignment PIN_AK21 -to GPIO_0[23]
+set_location_assignment PIN_AD19 -to GPIO_0[24]
+set_location_assignment PIN_AD20 -to GPIO_0[25]
+set_location_assignment PIN_AE18 -to GPIO_0[26]
+set_location_assignment PIN_AE19 -to GPIO_0[27]
+set_location_assignment PIN_AF20 -to GPIO_0[28]
+set_location_assignment PIN_AF21 -to GPIO_0[29]
+set_location_assignment PIN_AD17 -to GPIO_0[2]
+set_location_assignment PIN_AF19 -to GPIO_0[30]
+set_location_assignment PIN_AG21 -to GPIO_0[31]
+set_location_assignment PIN_AF18 -to GPIO_0[32]
+set_location_assignment PIN_AG20 -to GPIO_0[33]
+set_location_assignment PIN_AG18 -to GPIO_0[34]
+set_location_assignment PIN_AJ21 -to GPIO_0[35]
+set_location_assignment PIN_Y18 -to GPIO_0[3]
+set_location_assignment PIN_AK16 -to GPIO_0[4]
+set_location_assignment PIN_AK18 -to GPIO_0[5]
+set_location_assignment PIN_AK19 -to GPIO_0[6]
+set_location_assignment PIN_AJ19 -to GPIO_0[7]
+set_location_assignment PIN_AJ17 -to GPIO_0[8]
+set_location_assignment PIN_AJ16 -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+
+set_location_assignment PIN_AB17 -to GPIO_1[0]
+set_location_assignment PIN_AG26 -to GPIO_1[10]
+set_location_assignment PIN_AH24 -to GPIO_1[11]
+set_location_assignment PIN_AH27 -to GPIO_1[12]
+set_location_assignment PIN_AJ27 -to GPIO_1[13]
+set_location_assignment PIN_AK29 -to GPIO_1[14]
+set_location_assignment PIN_AK28 -to GPIO_1[15]
+set_location_assignment PIN_AK27 -to GPIO_1[16]
+set_location_assignment PIN_AJ26 -to GPIO_1[17]
+set_location_assignment PIN_AK26 -to GPIO_1[18]
+set_location_assignment PIN_AH25 -to GPIO_1[19]
+set_location_assignment PIN_AA21 -to GPIO_1[1]
+set_location_assignment PIN_AJ25 -to GPIO_1[20]
+set_location_assignment PIN_AJ24 -to GPIO_1[21]
+set_location_assignment PIN_AK24 -to GPIO_1[22]
+set_location_assignment PIN_AG23 -to GPIO_1[23]
+set_location_assignment PIN_AK23 -to GPIO_1[24]
+set_location_assignment PIN_AH23 -to GPIO_1[25]
+set_location_assignment PIN_AK22 -to GPIO_1[26]
+set_location_assignment PIN_AJ22 -to GPIO_1[27]
+set_location_assignment PIN_AH22 -to GPIO_1[28]
+set_location_assignment PIN_AG22 -to GPIO_1[29]
+set_location_assignment PIN_AB21 -to GPIO_1[2]
+set_location_assignment PIN_AF24 -to GPIO_1[30]
+set_location_assignment PIN_AF23 -to GPIO_1[31]
+set_location_assignment PIN_AE22 -to GPIO_1[32]
+set_location_assignment PIN_AD21 -to GPIO_1[33]
+set_location_assignment PIN_AA20 -to GPIO_1[34]
+set_location_assignment PIN_AC22 -to GPIO_1[35]
+set_location_assignment PIN_AC23 -to GPIO_1[3]
+set_location_assignment PIN_AD24 -to GPIO_1[4]
+set_location_assignment PIN_AE23 -to GPIO_1[5]
+set_location_assignment PIN_AE24 -to GPIO_1[6]
+set_location_assignment PIN_AF25 -to GPIO_1[7]
+set_location_assignment PIN_AF26 -to GPIO_1[8]
+set_location_assignment PIN_AG25 -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# IRDA
+#============================================================
+set_location_assignment PIN_AA30 -to IRDA_RXD
+set_location_assignment PIN_AB30 -to IRDA_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# PS2
+#============================================================
+set_location_assignment PIN_AD7 -to PS2_CLK
+set_location_assignment PIN_AE7 -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+
+set_location_assignment PIN_AD9 -to PS2_CLK2
+set_location_assignment PIN_AE9 -to PS2_DAT2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# TD
+#============================================================
+set_location_assignment PIN_H15 -to TD_CLK27
+set_location_assignment PIN_D2 -to TD_DATA[0]
+set_location_assignment PIN_B1 -to TD_DATA[1]
+set_location_assignment PIN_E2 -to TD_DATA[2]
+set_location_assignment PIN_B2 -to TD_DATA[3]
+set_location_assignment PIN_D1 -to TD_DATA[4]
+set_location_assignment PIN_E1 -to TD_DATA[5]
+set_location_assignment PIN_C2 -to TD_DATA[6]
+set_location_assignment PIN_B3 -to TD_DATA[7]
+set_location_assignment PIN_A5 -to TD_HS
+set_location_assignment PIN_F6 -to TD_RESET_N
+set_location_assignment PIN_A3 -to TD_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
+
+#============================================================
+# USB
+#============================================================
+set_location_assignment PIN_AF4 -to USB_B2_CLK
+set_location_assignment PIN_AH4 -to USB_B2_DATA[0]
+set_location_assignment PIN_AH3 -to USB_B2_DATA[1]
+set_location_assignment PIN_AJ2 -to USB_B2_DATA[2]
+set_location_assignment PIN_AJ1 -to USB_B2_DATA[3]
+set_location_assignment PIN_AH2 -to USB_B2_DATA[4]
+set_location_assignment PIN_AG3 -to USB_B2_DATA[5]
+set_location_assignment PIN_AG2 -to USB_B2_DATA[6]
+set_location_assignment PIN_AG1 -to USB_B2_DATA[7]
+set_location_assignment PIN_AF5 -to USB_EMPTY
+set_location_assignment PIN_AG5 -to USB_FULL
+set_location_assignment PIN_AF6 -to USB_OE_N
+set_location_assignment PIN_AG6 -to USB_RD_N
+set_location_assignment PIN_AG7 -to USB_RESET_N
+set_location_assignment PIN_AG8 -to USB_SCL
+set_location_assignment PIN_AF8 -to USB_SDA
+set_location_assignment PIN_AH5 -to USB_WR_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_B13 -to VGA_B[0]
+set_location_assignment PIN_G13 -to VGA_B[1]
+set_location_assignment PIN_H13 -to VGA_B[2]
+set_location_assignment PIN_F14 -to VGA_B[3]
+set_location_assignment PIN_H14 -to VGA_B[4]
+set_location_assignment PIN_F15 -to VGA_B[5]
+set_location_assignment PIN_G15 -to VGA_B[6]
+set_location_assignment PIN_J14 -to VGA_B[7]
+set_location_assignment PIN_F10 -to VGA_BLANK_N
+set_location_assignment PIN_A11 -to VGA_CLK
+set_location_assignment PIN_J9 -to VGA_G[0]
+set_location_assignment PIN_J10 -to VGA_G[1]
+set_location_assignment PIN_H12 -to VGA_G[2]
+set_location_assignment PIN_G10 -to VGA_G[3]
+set_location_assignment PIN_G11 -to VGA_G[4]
+set_location_assignment PIN_G12 -to VGA_G[5]
+set_location_assignment PIN_F11 -to VGA_G[6]
+set_location_assignment PIN_E11 -to VGA_G[7]
+set_location_assignment PIN_B11 -to VGA_HS
+set_location_assignment PIN_A13 -to VGA_R[0]
+set_location_assignment PIN_C13 -to VGA_R[1]
+set_location_assignment PIN_E13 -to VGA_R[2]
+set_location_assignment PIN_B12 -to VGA_R[3]
+set_location_assignment PIN_C12 -to VGA_R[4]
+set_location_assignment PIN_D12 -to VGA_R[5]
+set_location_assignment PIN_E12 -to VGA_R[6]
+set_location_assignment PIN_F13 -to VGA_R[7]
+set_location_assignment PIN_C10 -to VGA_SYNC_N
+set_location_assignment PIN_D11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+
+#============================================================
+# HPS
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_BA[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CKE
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_N
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_CK_P
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_CS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DM[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_ODT
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RAS_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_RESET_N
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to HPS_DDR3_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
+set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[0]
+set_instance_assignment -name io_standard "3.3-V LVTTL" -to HPS_GPIO[1]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_BA[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CAS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_CS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_ODT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RAS_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_WE_N
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to HPS_DDR3_RESET_N
+
+set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_P
+set_instance_assignment -name D5_DELAY 2 -to HPS_DDR3_CK_N
+
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3]
+
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[4]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[5]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[6]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[7]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[8]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[9]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[10]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[11]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[12]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[13]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[14]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[15]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[16]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[17]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[18]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[19]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[20]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[21]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[22]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[23]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[24]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[25]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[26]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[27]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[28]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[29]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[30]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[31]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_P
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to HPS_DDR3_CK_N
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DM[3]
+
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[5]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[6]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[7]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[8]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[9]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[10]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[11]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[12]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[13]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[14]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[15]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[16]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[17]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[18]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[19]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[20]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[21]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[22]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[23]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[24]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[25]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[26]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[27]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[28]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[29]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[30]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQ[31]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DM[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_P[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_DQS_N[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[10]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[11]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[12]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[13]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[14]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[5]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[6]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[7]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[8]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ADDR[9]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_BA[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CAS_N
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CKE
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CS_N
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_ODT
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RAS_N
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_WE_N
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_RESET_N
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_P
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to HPS_DDR3_CK_N
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+
diff --git a/task1/.gitignore b/task1/.gitignore new file mode 100644 index 0000000..b0345dc --- /dev/null +++ b/task1/.gitignore @@ -0,0 +1,18 @@ +.DS_Store +transcript +tcl_stacktrace.txt +c5_pin_model_dump.txt +*.mti +*.mpf +*.wlf +*.qdb +*.qpg +*.qtl +*.qpf +*.sof +*.bak +work/ +db/ +incremental_db/ +simulation/ +output_files/ diff --git a/task1/vga_demo.sv b/task1/vga_demo.sv new file mode 100644 index 0000000..88aa64e --- /dev/null +++ b/task1/vga_demo.sv @@ -0,0 +1,29 @@ +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +module vga_demo(input logic CLOCK_50, input logic [3:0] KEY, input logic [9:0] SW, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK, + output logic [7:0] VGA_X, output logic [6:0] VGA_Y, + output logic [2:0] VGA_COLOUR, output logic VGA_PLOT); + +logic [9:0] VGA_R_10; +logic [9:0] VGA_G_10; +logic [9:0] VGA_B_10; +logic VGA_BLANK, VGA_SYNC; + +assign VGA_R = VGA_R_10[9:2]; +assign VGA_G = VGA_G_10[9:2]; +assign VGA_B = VGA_B_10[9:2]; + +assign VGA_X = {3'b0,SW[4:0]}; +assign VGA_Y = {2'b0,SW[9:5]}; +assign VGA_PLOT = ~KEY[0]; +assign VGA_COLOUR = SW[2:0]; + +vga_adapter#(.RESOLUTION("160x120")) vga_u0(.resetn(KEY[3]), .clock(CLOCK_50), .colour(SW[2:0]), + .x({3'b0,SW[4:0]}), .y({2'b0,SW[9:5]}), .plot(~KEY[0]), + .VGA_R(VGA_R_10), .VGA_G(VGA_G_10), .VGA_B(VGA_B_10), + .*); +endmodule: vga_demo diff --git a/task2/.gitignore b/task2/.gitignore new file mode 100644 index 0000000..b0345dc --- /dev/null +++ b/task2/.gitignore @@ -0,0 +1,18 @@ +.DS_Store +transcript +tcl_stacktrace.txt +c5_pin_model_dump.txt +*.mti +*.mpf +*.wlf +*.qdb +*.qpg +*.qtl +*.qpf +*.sof +*.bak +work/ +db/ +incremental_db/ +simulation/ +output_files/ diff --git a/task2/README.md b/task2/README.md new file mode 100644 index 0000000..700d8b9 --- /dev/null +++ b/task2/README.md @@ -0,0 +1,13 @@ +# Contributions +List of contributions made by members of the team. + +It is highly recommended that you each work individually on this specific task. However, only one solution needs to be pushed to GitHub. + +## Contributions made by ABC DEF +- contribution 1 +- contribution 2 + +## Contributions made by TUV XYZ +- contribution 1 +- contribution 2 + diff --git a/task2/fillscreen.sv b/task2/fillscreen.sv new file mode 100644 index 0000000..323e7a5 --- /dev/null +++ b/task2/fillscreen.sv @@ -0,0 +1,7 @@ +module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour, + input logic start, output logic done, + output logic [7:0] vga_x, output logic [6:0] vga_y, + output logic [2:0] vga_colour, output logic vga_plot); + // fill the screen +endmodule + diff --git a/task2/task2.sv b/task2/task2.sv new file mode 100644 index 0000000..8389348 --- /dev/null +++ b/task2/task2.sv @@ -0,0 +1,12 @@ +module task2(input logic CLOCK_50, input logic [3:0] KEY, + input logic [9:0] SW, output logic [9:0] LEDR, + output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, + output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK, + output logic [7:0] VGA_X, output logic [6:0] VGA_Y, + output logic [2:0] VGA_COLOUR, output logic VGA_PLOT); + + // instantiate and connect the VGA adapter and your module + +endmodule: task2 diff --git a/task2/tb_rtl_fillscreen.sv b/task2/tb_rtl_fillscreen.sv new file mode 100644 index 0000000..0c8013b --- /dev/null +++ b/task2/tb_rtl_fillscreen.sv @@ -0,0 +1,5 @@ +module tb_rtl_fillscreen(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_fillscreen diff --git a/task2/tb_rtl_task2.sv b/task2/tb_rtl_task2.sv new file mode 100644 index 0000000..736b1f6 --- /dev/null +++ b/task2/tb_rtl_task2.sv @@ -0,0 +1,5 @@ +module tb_rtl_task2(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_task2 diff --git a/task2/tb_syn_fillscreen.sv b/task2/tb_syn_fillscreen.sv new file mode 100644 index 0000000..11d80a4 --- /dev/null +++ b/task2/tb_syn_fillscreen.sv @@ -0,0 +1,5 @@ +module tb_syn_fillscreen(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_fillscreen diff --git a/task2/tb_syn_task2.sv b/task2/tb_syn_task2.sv new file mode 100644 index 0000000..31aa3a9 --- /dev/null +++ b/task2/tb_syn_task2.sv @@ -0,0 +1,5 @@ +module tb_syn_task2(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_task2 diff --git a/task2/tb_task2.sv b/task2/tb_task2.sv new file mode 100644 index 0000000..ceb4e98 --- /dev/null +++ b/task2/tb_task2.sv @@ -0,0 +1,5 @@ +module tb_task2(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_task2 diff --git a/task3/.gitignore b/task3/.gitignore new file mode 100644 index 0000000..b0345dc --- /dev/null +++ b/task3/.gitignore @@ -0,0 +1,18 @@ +.DS_Store +transcript +tcl_stacktrace.txt +c5_pin_model_dump.txt +*.mti +*.mpf +*.wlf +*.qdb +*.qpg +*.qtl +*.qpf +*.sof +*.bak +work/ +db/ +incremental_db/ +simulation/ +output_files/ diff --git a/task3/README.md b/task3/README.md new file mode 100644 index 0000000..7a55339 --- /dev/null +++ b/task3/README.md @@ -0,0 +1,12 @@ +# Contributions +List of contributions made by members of the team. + +## Contributions made by ABC DEF +- contribution 1 +- contribution 2 + +## Contributions made by TUV XYZ +- contribution 1 +- contribution 2 + + diff --git a/task3/circle.sv b/task3/circle.sv new file mode 100644 index 0000000..112426d --- /dev/null +++ b/task3/circle.sv @@ -0,0 +1,8 @@ +module circle(input logic clk, input logic rst_n, input logic [2:0] colour, + input logic [7:0] centre_x, input logic [6:0] centre_y, input logic [7:0] radius, + input logic start, output logic done, + output logic [7:0] vga_x, output logic [6:0] vga_y, + output logic [2:0] vga_colour, output logic vga_plot); + // draw the circle +endmodule + diff --git a/task3/task3.sv b/task3/task3.sv new file mode 100644 index 0000000..d22ae1c --- /dev/null +++ b/task3/task3.sv @@ -0,0 +1,12 @@ +module task3(input logic CLOCK_50, input logic [3:0] KEY, + input logic [9:0] SW, output logic [9:0] LEDR, + output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, + output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK, + output logic [7:0] VGA_X, output logic [6:0] VGA_Y, + output logic [2:0] VGA_COLOUR, output logic VGA_PLOT); + + // instantiate and connect the VGA adapter and your module + +endmodule: task3 diff --git a/task3/tb_rtl_circle.sv b/task3/tb_rtl_circle.sv new file mode 100644 index 0000000..8f1fbaa --- /dev/null +++ b/task3/tb_rtl_circle.sv @@ -0,0 +1,5 @@ +module tb_rtl_circle(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_circle diff --git a/task3/tb_rtl_task3.sv b/task3/tb_rtl_task3.sv new file mode 100644 index 0000000..3404a06 --- /dev/null +++ b/task3/tb_rtl_task3.sv @@ -0,0 +1,5 @@ +module tb_rtl_task3(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_task3 diff --git a/task3/tb_syn_circle.sv b/task3/tb_syn_circle.sv new file mode 100644 index 0000000..9134b68 --- /dev/null +++ b/task3/tb_syn_circle.sv @@ -0,0 +1,5 @@ +module tb_syn_circle(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_circle diff --git a/task3/tb_syn_task3.sv b/task3/tb_syn_task3.sv new file mode 100644 index 0000000..fe0a6f4 --- /dev/null +++ b/task3/tb_syn_task3.sv @@ -0,0 +1,5 @@ +module tb_syn_task3(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_task3 diff --git a/task3/tb_task3.sv b/task3/tb_task3.sv new file mode 100644 index 0000000..1d5c655 --- /dev/null +++ b/task3/tb_task3.sv @@ -0,0 +1,5 @@ +module tb_task3(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_task3 diff --git a/task4/.gitignore b/task4/.gitignore new file mode 100644 index 0000000..b0345dc --- /dev/null +++ b/task4/.gitignore @@ -0,0 +1,18 @@ +.DS_Store +transcript +tcl_stacktrace.txt +c5_pin_model_dump.txt +*.mti +*.mpf +*.wlf +*.qdb +*.qpg +*.qtl +*.qpf +*.sof +*.bak +work/ +db/ +incremental_db/ +simulation/ +output_files/ diff --git a/task4/README.md b/task4/README.md new file mode 100644 index 0000000..7a55339 --- /dev/null +++ b/task4/README.md @@ -0,0 +1,12 @@ +# Contributions +List of contributions made by members of the team. + +## Contributions made by ABC DEF +- contribution 1 +- contribution 2 + +## Contributions made by TUV XYZ +- contribution 1 +- contribution 2 + + diff --git a/task4/reuleaux.sv b/task4/reuleaux.sv new file mode 100644 index 0000000..abcde5e --- /dev/null +++ b/task4/reuleaux.sv @@ -0,0 +1,8 @@ +module reuleaux(input logic clk, input logic rst_n, input logic [2:0] colour, + input logic [7:0] centre_x, input logic [6:0] centre_y, input logic [7:0] diameter, + input logic start, output logic done, + output logic [7:0] vga_x, output logic [6:0] vga_y, + output logic [2:0] vga_colour, output logic vga_plot); + // draw the Reuleaux triangle +endmodule + diff --git a/task4/task4.sv b/task4/task4.sv new file mode 100644 index 0000000..71d43be --- /dev/null +++ b/task4/task4.sv @@ -0,0 +1,12 @@ +module task4(input logic CLOCK_50, input logic [3:0] KEY, + input logic [9:0] SW, output logic [9:0] LEDR, + output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2, + output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5, + output logic [7:0] VGA_R, output logic [7:0] VGA_G, output logic [7:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_CLK, + output logic [7:0] VGA_X, output logic [6:0] VGA_Y, + output logic [2:0] VGA_COLOUR, output logic VGA_PLOT); + + // instantiate and connect the VGA adapter and your module + +endmodule: task4 diff --git a/task4/tb_rtl_reuleaux.sv b/task4/tb_rtl_reuleaux.sv new file mode 100644 index 0000000..4e77c33 --- /dev/null +++ b/task4/tb_rtl_reuleaux.sv @@ -0,0 +1,5 @@ +module tb_rtl_reuleaux(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_reuleaux diff --git a/task4/tb_rtl_task4.sv b/task4/tb_rtl_task4.sv new file mode 100644 index 0000000..47f6810 --- /dev/null +++ b/task4/tb_rtl_task4.sv @@ -0,0 +1,5 @@ +module tb_rtl_task4(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_rtl_task4 diff --git a/task4/tb_syn_reuleaux.sv b/task4/tb_syn_reuleaux.sv new file mode 100644 index 0000000..d39f0bb --- /dev/null +++ b/task4/tb_syn_reuleaux.sv @@ -0,0 +1,5 @@ +module tb_syn_reuleaux(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_reuleaux diff --git a/task4/tb_syn_task4.sv b/task4/tb_syn_task4.sv new file mode 100644 index 0000000..8c66b3f --- /dev/null +++ b/task4/tb_syn_task4.sv @@ -0,0 +1,5 @@ +module tb_syn_task4(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_syn_task4 diff --git a/task4/tb_task4.sv b/task4/tb_task4.sv new file mode 100644 index 0000000..04f882f --- /dev/null +++ b/task4/tb_task4.sv @@ -0,0 +1,5 @@ +module tb_task4(); + +// Your testbench goes here. Our toplevel will give up after 1,000,000 ticks. + +endmodule: tb_task4 diff --git a/vga-core/de1_vga_gui.tcl b/vga-core/de1_vga_gui.tcl new file mode 100644 index 0000000..a6a3a4a --- /dev/null +++ b/vga-core/de1_vga_gui.tcl @@ -0,0 +1,107 @@ +# vim: set sw=4 ai cin et: + +# NOTE: this must be sychronized with VGA adaptor module + + +if { [namespace exists ::de1vga] } { namespace delete ::de1vga } + +namespace eval ::de1vga { + namespace eval var { + set zoom 4 + set width 160 + set height 120 + set bg "#808080" + set count 0 + } + + + proc init {} { + if ({[winfo exists .de1vga]}) { destroy .de1vga } + + toplevel .de1vga -padx 5 -pady 5 + wm title .de1vga "fake VGA screen" + + frame .de1vga.draw + pack .de1vga.draw -expand 1 -fill both + + frame .de1vga.status + button .de1vga.status.reset -width 5 -relief ridge -text "CLEAR" -command [namespace code reset] + label .de1vga.status.count_legend -text " count:" + label .de1vga.status.count_val -relief groove -width 10 + + label .de1vga.status.drawn_legend -text "last:" + label .de1vga.status.drawn_pos -relief groove -width 7 + label .de1vga.status.click_legend -text " clicked:" + label .de1vga.status.click_pos -relief groove -width 7 + label .de1vga.status.mouse_legend -text " mouse:" + label .de1vga.status.mouse_pos -relief groove -width 7 + pack .de1vga.status.reset .de1vga.status.count_legend .de1vga.status.count_val -side left + pack .de1vga.status.mouse_pos .de1vga.status.mouse_legend .de1vga.status.click_pos .de1vga.status.click_legend \ + .de1vga.status.drawn_pos .de1vga.status.drawn_legend -side right + pack .de1vga.status -side bottom -fill x + .de1vga.status.drawn_pos configure -text "-,-" + .de1vga.status.mouse_pos configure -text "-,-" + .de1vga.status.click_pos configure -text "-,-" + + set w [expr $var::width * $var::zoom] + set h [expr {$var::height * $var::zoom}] + canvas .de1vga.draw.c -width $w -height $h -bg $var::bg + pack .de1vga.draw.c -expand 1 -fill both + bind .de1vga.draw.c <Motion> [namespace code { show_mouse %x %y }] + bind .de1vga.draw.c <ButtonPress> [namespace code { show_click %x %y }] + bind .de1vga.draw.c <Leave> [namespace code { .de1vga.status.mouse_pos configure -text "-,-" }] + } + + proc reset {} { + .de1vga.draw.c create rectangle 0 0 [expr $var::width * $var::zoom - 1] [expr $var::height * $var::zoom - 1] -outline $var::bg -fill $var::bg + set var::count 0 + .de1vga.status.count_val configure -text "$var::count" + .de1vga.status.drawn_pos configure -text "-,-" + } + + proc rgb_to_hex {c} { + set b [expr ($c & 1) * 255] + set g [expr (($c >> 1) & 1) * 255] + set r [expr (($c >> 2) & 1) * 255] + return [format "#%02x%02x%02x" $r $g $b] + } + + proc plot {x y c} { + if !({[winfo exists .de1vga]}) {init} + + set x [string tolower $x] + set y [string tolower $y] + set c [string tolower $c] + if { [string equal $x "x"] || [string equal $x "z" ]} { return } + if { [string equal $y "x"] || [string equal $y "z" ]} { return } + if { [string equal $c "x"] || [string equal $c "z" ]} { return } + if {[expr $x < 0]} { return } + if {[expr $x >= $var::width]} { return } + if {[expr $y < 0]} { return } + if {[expr $y >= $var::height]} { return } + if !({[winfo exists .de1vga]}) { init } + set x0 [expr $x * $var::zoom] + set y0 [expr $y * $var::zoom] + set x1 [expr ($x+1) * $var::zoom - 1] + set y1 [expr ($y+1) * $var::zoom - 1] + set clr [rgb_to_hex $c] + .de1vga.draw.c create rectangle $x0 $y0 $x1 $y1 -outline $clr -fill $clr + incr var::count + .de1vga.status.count_val configure -text "$var::count" + .de1vga.status.drawn_pos configure -text "$x,$y:$c" + } + + proc show_mouse {x0 y0} { + set x [expr $x0 / $var::zoom] + set y [expr $y0 / $var::zoom] + .de1vga.status.mouse_pos configure -text "$x,$y" + } + + proc show_click {x0 y0} { + set x [expr $x0 / $var::zoom] + set y [expr $y0 / $var::zoom] + .de1vga.status.click_pos configure -text "$x,$y" + } +} + +namespace inscope ::de1vga init diff --git a/vga-core/vga_adapter.sv b/vga-core/vga_adapter.sv new file mode 100644 index 0000000..3b9209c --- /dev/null +++ b/vga-core/vga_adapter.sv @@ -0,0 +1,283 @@ +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +/* VGA Adapter + * ---------------- + * + * This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate + * a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz. + * It is designed for easy use in an early digital logic design course to facilitate student + * projects on the Altera DE2 Educational board. + * + * This implementation of the VGA adapter can display images of varying colour depth at a resolution of + * 320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip + * memory used by the adapter. The following table shows the number of bits of on-chip memory used by + * the adapter in various resolutions and colour depths. + * + * ------------------------------------------------------------------------------------------------------------------------------- + * Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours | + * ------------------------------------------------------------------------------------------------------------------------------- + * 160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 | + * 320x240 | 78600 | 230400 | ############## Does not fit ############################################################## | + * ------------------------------------------------------------------------------------------------------------------------------- + * + * By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of + * the other modes, the adapter must be instantiated with specific parameters. These parameters are: + * - RESOLUTION - a string that should be either "320x240" or "160x120". + * - MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE" + * otherwise. + * - BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour + * (R,G,B). A default value of 1 indicates that 1 bit will be used for red + * channel, 1 for green channel and 1 for blue channel. This allows 8 colours + * to be used. + * + * In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter + * refers to a memory initilization file (MIF) which contains the initial contents of video memory. + * By specifying the initial contents of the memory we can force the adapter to initially display an + * image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only + * be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen, + * the video memory will be altered and screen contents will be changed. In order to restore the background + * image your circuti will have to redraw the background image pixel by pixel, or you will have to + * reprogram the DE2 board, thus allowing the video memory to be rewritten. + * + * To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for + * inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter + * will change the contents of the video memory for the pixel at location (X,Y). At the next redraw + * cycle the VGA controller will update the contants of the screen by reading the video memory and copying + * it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the + * contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus, + * the video memory should not be used for other purposes as it may interfere with the operation of the + * VGA Adapter. + * + * As a final note, ensure that the following conditions are met when using this module: + * 1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change + * the amount of memory you can use, the clock generation mechanism, as well as pin assignments required + * to properly drive the VGA digital-to-analog converter. + * 2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the + * Altera DE2 board as specified by the DE2_pin_assignments.csv file. + * 3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board + * PIN_N2 is the source for the 50MHz clock. + * + * During compilation with Quartus II you may receive the following warnings: + * - Warning: Variable or input pin "clocken1" is defined but never used + * - Warning: Pin "VGA_SYNC" stuck at VCC + * - Warning: Found xx output pins without output pin load capacitance assignment + * These warnings can be ignored. The first warning is generated, because the software generated + * memory module contains an input called "clocken1" and it does not drive logic. The second warning + * indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is + * generated for the purposes of power analysis. It will persist unless the output pins are assigned + * output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module. + * + * If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may + * cause your circuit to malfunction. + * + * NOTES/REVISIONS: + * July 10, 2007 - Modified the original version of the VGA Adapter written by Sam Vafaee in 2006. The module + * now supports 2 different resolutions as well as uses half the memory compared to prior + * implementation. Also, all settings for the module can be specified from the point + * of instantiation, rather than by modifying the source code. (Tomasz S. Czajkowski) + */ + +module vga_adapter( + resetn, + clock, + colour, + x, y, plot, + /* Signals for the DAC to drive the monitor. */ + VGA_R, + VGA_G, + VGA_B, + VGA_HS, + VGA_VS, + VGA_BLANK, + VGA_SYNC, + VGA_CLK); + + parameter BITS_PER_COLOUR_CHANNEL = 1; + /* The number of bits per colour channel used to represent the colour of each pixel. A value + * of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity + * of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours. + * In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL ) colours. The number of colours is + * limited by the screen resolution and the amount of on-chip memory available on the target device. + */ + + parameter MONOCHROME = "FALSE"; + /* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce + * the amount of memory you will use by a factor of 3. */ + + parameter RESOLUTION = "320x240"; + /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on + * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution). + * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary + * to reduce the resolution for the Video Memory to fit within the on-chip memory limits. + */ + + parameter BACKGROUND_IMAGE = "background.mif"; + /* The initial screen displayed when the circuit is first programmed onto the DE2 board can be + * defined useing an MIF file. The file contains the initial colour for each pixel on the screen + * and is placed in the Video Memory (VideoMemory module) upon programming. Note that resetting the + * VGA Adapter will not cause the Video Memory to revert to the specified image. */ + + parameter USING_DE1 = "FALSE"; + /* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences + * between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if + * you are running your circuit on a DE1 board. */ + + /*****************************************************************************/ + /* Declare inputs and outputs. */ + /*****************************************************************************/ + input resetn; + input clock; + + /* The colour input can be either 1 bit or 3*BITS_PER_COLOUR_CHANNEL bits wide, depending on + * the setting of the MONOCHROME parameter. + */ + input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] colour; + + /* Specify the number of bits required to represent an (X,Y) coordinate on the screen for + * a given resolution. + */ + input [((RESOLUTION == "320x240") ? (8) : (7)):0] x; + input [((RESOLUTION == "320x240") ? (7) : (6)):0] y; + + /* When plot is high then at the next positive edge of the clock the pixel at (x,y) will change to + * a new colour, defined by the value of the colour input. + */ + input plot; + + /* These outputs drive the VGA display. The VGA_CLK is also used to clock the FSM responsible for + * controlling the data transferred to the DAC driving the monitor. */ + output [9:0] VGA_R; + output [9:0] VGA_G; + output [9:0] VGA_B; + output VGA_HS; + output VGA_VS; + output VGA_BLANK; + output VGA_SYNC; + output VGA_CLK; + + /*****************************************************************************/ + /* Declare local signals here. */ + /*****************************************************************************/ + + wire valid_160x120; + wire valid_320x240; + /* Set to 1 if the specified coordinates are in a valid range for a given resolution.*/ + + wire writeEn; + /* This is a local signal that allows the Video Memory contents to be changed. + * It depends on the screen resolution, the values of X and Y inputs, as well as + * the state of the plot signal. + */ + + wire [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] to_ctrl_colour; + /* Pixel colour read by the VGA controller */ + + wire [((RESOLUTION == "320x240") ? (16) : (14)):0] user_to_video_memory_addr; + /* This bus specifies the address in memory the user must write + * data to in order for the pixel intended to appear at location (X,Y) to be displayed + * at the correct location on the screen. + */ + + wire [((RESOLUTION == "320x240") ? (16) : (14)):0] controller_to_video_memory_addr; + /* This bus specifies the address in memory the vga controller must read data from + * in order to determine the colour of a pixel located at coordinate (X,Y) of the screen. + */ + + wire clock_25; + /* 25MHz clock generated by dividing the input clock frequency by 2. */ + + wire vcc, gnd; + + /*****************************************************************************/ + /* Instances of modules for the VGA adapter. */ + /*****************************************************************************/ + assign vcc = 1'b1; + assign gnd = 1'b0; + + vga_address_translator user_input_translator( + .x(x), .y(y), .mem_address(user_to_video_memory_addr) ); + defparam user_input_translator.RESOLUTION = RESOLUTION; + /* Convert user coordinates into a memory address. */ + + assign valid_160x120 = (({1'b0, x} >= 0) & ({1'b0, x} < 160) & ({1'b0, y} >= 0) & ({1'b0, y} < 120)) & (RESOLUTION == "160x120"); + assign valid_320x240 = (({1'b0, x} >= 0) & ({1'b0, x} < 320) & ({1'b0, y} >= 0) & ({1'b0, y} < 240)) & (RESOLUTION == "320x240"); + assign writeEn = (plot) & (valid_160x120 | valid_320x240); + /* Allow the user to plot a pixel if and only if the (X,Y) coordinates supplied are in a valid range. */ + + /* Create video memory. */ + altsyncram VideoMemory ( + .wren_a (writeEn), + .wren_b (gnd), + .clock0 (clock), // write clock + .clock1 (clock_25), // read clock + .clocken0 (vcc), // write enable clock + .clocken1 (vcc), // read enable clock + .address_a (user_to_video_memory_addr), + .address_b (controller_to_video_memory_addr), + .data_a (colour), // data in + .q_b (to_ctrl_colour) // data out + ); + defparam + VideoMemory.width_a = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1), + VideoMemory.width_b = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1), + VideoMemory.intended_device_family = "Cyclone II", + VideoMemory.operation_mode = "DUAL_PORT", + VideoMemory.widthad_a = ((RESOLUTION == "320x240") ? (17) : (15)), + VideoMemory.numwords_a = ((RESOLUTION == "320x240") ? (76800) : (19200)), + VideoMemory.widthad_b = ((RESOLUTION == "320x240") ? (17) : (15)), + VideoMemory.numwords_b = ((RESOLUTION == "320x240") ? (76800) : (19200)), + VideoMemory.outdata_reg_b = "CLOCK1", + VideoMemory.address_reg_b = "CLOCK1", + VideoMemory.clock_enable_input_a = "BYPASS", + VideoMemory.clock_enable_input_b = "BYPASS", + VideoMemory.clock_enable_output_b = "BYPASS", + VideoMemory.power_up_uninitialized = "TRUE"; + + vga_pll mypll(clock, clock_25); + /* This module generates a clock with half the frequency of the input clock. + * For the VGA adapter to operate correctly the clock signal 'clock' must be + * a 50MHz clock. The derived clock, which will then operate at 25MHz, is + * required to set the monitor into the 640x480@60Hz display mode (also known as + * the VGA mode). + */ + + vga_controller controller( + .vga_clock(clock_25), + .resetn(resetn), + .pixel_colour(to_ctrl_colour), + .memory_address(controller_to_video_memory_addr), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_HS(VGA_HS), + .VGA_VS(VGA_VS), + .VGA_BLANK(VGA_BLANK), + .VGA_SYNC(VGA_SYNC), + .VGA_CLK(VGA_CLK) + ); + defparam controller.BITS_PER_COLOUR_CHANNEL = BITS_PER_COLOUR_CHANNEL ; + defparam controller.MONOCHROME = MONOCHROME; + defparam controller.RESOLUTION = RESOLUTION; + defparam controller.USING_DE1 = USING_DE1; + + // synthesis translate_off + always @(posedge clock, negedge resetn) begin + if (resetn === 1'b0) begin +`ifdef MODEL_TECH + mti_fli::mti_Command("if { [namespace exists ::de1vga] } { ::de1vga::reset } else { echo \"VGA RESET\" }"); +`else + $display("VGA RESET"); +`endif + end else if (plot === 1'b1) begin +`ifdef MODEL_TECH + mti_fli::mti_Command($sformatf("if { [namespace exists ::de1vga] } { ::de1vga::plot %0d %0d %0d } else { echo \"VGA PLOT %0d,%0d %0d\" }", x, y, colour, x, y, colour)); +`else + $display("VGA PLOT %0d,%0d %0d", x, y, colour); +`endif + end + end + // synthesis translate_on + +endmodule diff --git a/vga-core/vga_adapter.v b/vga-core/vga_adapter.v new file mode 100644 index 0000000..83e7413 --- /dev/null +++ b/vga-core/vga_adapter.v @@ -0,0 +1,263 @@ +/* VGA Adapter
+ * ----------------
+ *
+ * This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate
+ * a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz.
+ * It is designed for easy use in an early digital logic design course to facilitate student
+ * projects on the Altera DE2 Educational board.
+ *
+ * This implementation of the VGA adapter can display images of varying colour depth at a resolution of
+ * 320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip
+ * memory used by the adapter. The following table shows the number of bits of on-chip memory used by
+ * the adapter in various resolutions and colour depths.
+ *
+ * -------------------------------------------------------------------------------------------------------------------------------
+ * Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours |
+ * -------------------------------------------------------------------------------------------------------------------------------
+ * 160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 |
+ * 320x240 | 78600 | 230400 | ############## Does not fit ############################################################## |
+ * -------------------------------------------------------------------------------------------------------------------------------
+ *
+ * By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of
+ * the other modes, the adapter must be instantiated with specific parameters. These parameters are:
+ * - RESOLUTION - a string that should be either "320x240" or "160x120".
+ * - MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE"
+ * otherwise.
+ * - BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour
+ * (R,G,B). A default value of 1 indicates that 1 bit will be used for red
+ * channel, 1 for green channel and 1 for blue channel. This allows 8 colours
+ * to be used.
+ *
+ * In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter
+ * refers to a memory initilization file (MIF) which contains the initial contents of video memory.
+ * By specifying the initial contents of the memory we can force the adapter to initially display an
+ * image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only
+ * be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen,
+ * the video memory will be altered and screen contents will be changed. In order to restore the background
+ * image your circuti will have to redraw the background image pixel by pixel, or you will have to
+ * reprogram the DE2 board, thus allowing the video memory to be rewritten.
+ *
+ * To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for
+ * inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter
+ * will change the contents of the video memory for the pixel at location (X,Y). At the next redraw
+ * cycle the VGA controller will update the contants of the screen by reading the video memory and copying
+ * it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the
+ * contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus,
+ * the video memory should not be used for other purposes as it may interfere with the operation of the
+ * VGA Adapter.
+ *
+ * As a final note, ensure that the following conditions are met when using this module:
+ * 1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change
+ * the amount of memory you can use, the clock generation mechanism, as well as pin assignments required
+ * to properly drive the VGA digital-to-analog converter.
+ * 2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the
+ * Altera DE2 board as specified by the DE2_pin_assignments.csv file.
+ * 3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board
+ * PIN_N2 is the source for the 50MHz clock.
+ *
+ * During compilation with Quartus II you may receive the following warnings:
+ * - Warning: Variable or input pin "clocken1" is defined but never used
+ * - Warning: Pin "VGA_SYNC" stuck at VCC
+ * - Warning: Found xx output pins without output pin load capacitance assignment
+ * These warnings can be ignored. The first warning is generated, because the software generated
+ * memory module contains an input called "clocken1" and it does not drive logic. The second warning
+ * indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is
+ * generated for the purposes of power analysis. It will persist unless the output pins are assigned
+ * output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module.
+ *
+ * If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may
+ * cause your circuit to malfunction.
+ *
+ * NOTES/REVISIONS:
+ * July 10, 2007 - Modified the original version of the VGA Adapter written by Sam Vafaee in 2006. The module
+ * now supports 2 different resolutions as well as uses half the memory compared to prior
+ * implementation. Also, all settings for the module can be specified from the point
+ * of instantiation, rather than by modifying the source code. (Tomasz S. Czajkowski)
+ */
+
+module vga_adapter(
+ resetn,
+ clock,
+ colour,
+ x, y, plot,
+ /* Signals for the DAC to drive the monitor. */
+ VGA_R,
+ VGA_G,
+ VGA_B,
+ VGA_HS,
+ VGA_VS,
+ VGA_BLANK,
+ VGA_SYNC,
+ VGA_CLK);
+
+ parameter BITS_PER_COLOUR_CHANNEL = 1;
+ /* The number of bits per colour channel used to represent the colour of each pixel. A value
+ * of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
+ * of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
+ * In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL ) colours. The number of colours is
+ * limited by the screen resolution and the amount of on-chip memory available on the target device.
+ */
+
+ parameter MONOCHROME = "FALSE";
+ /* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
+ * the amount of memory you will use by a factor of 3. */
+
+ parameter RESOLUTION = "320x240";
+ /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
+ * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
+ * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
+ * to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
+ */
+
+ parameter BACKGROUND_IMAGE = "background.mif";
+ /* The initial screen displayed when the circuit is first programmed onto the DE2 board can be
+ * defined useing an MIF file. The file contains the initial colour for each pixel on the screen
+ * and is placed in the Video Memory (VideoMemory module) upon programming. Note that resetting the
+ * VGA Adapter will not cause the Video Memory to revert to the specified image. */
+
+ parameter USING_DE1 = "FALSE";
+ /* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
+ * between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
+ * you are running your circuit on a DE1 board. */
+
+ /*****************************************************************************/
+ /* Declare inputs and outputs. */
+ /*****************************************************************************/
+ input resetn;
+ input clock;
+
+ /* The colour input can be either 1 bit or 3*BITS_PER_COLOUR_CHANNEL bits wide, depending on
+ * the setting of the MONOCHROME parameter.
+ */
+ input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] colour;
+
+ /* Specify the number of bits required to represent an (X,Y) coordinate on the screen for
+ * a given resolution.
+ */
+ input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
+ input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
+
+ /* When plot is high then at the next positive edge of the clock the pixel at (x,y) will change to
+ * a new colour, defined by the value of the colour input.
+ */
+ input plot;
+
+ /* These outputs drive the VGA display. The VGA_CLK is also used to clock the FSM responsible for
+ * controlling the data transferred to the DAC driving the monitor. */
+ output [9:0] VGA_R;
+ output [9:0] VGA_G;
+ output [9:0] VGA_B;
+ output VGA_HS;
+ output VGA_VS;
+ output VGA_BLANK;
+ output VGA_SYNC;
+ output VGA_CLK;
+
+ /*****************************************************************************/
+ /* Declare local signals here. */
+ /*****************************************************************************/
+
+ wire valid_160x120;
+ wire valid_320x240;
+ /* Set to 1 if the specified coordinates are in a valid range for a given resolution.*/
+
+ wire writeEn;
+ /* This is a local signal that allows the Video Memory contents to be changed.
+ * It depends on the screen resolution, the values of X and Y inputs, as well as
+ * the state of the plot signal.
+ */
+
+ wire [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] to_ctrl_colour;
+ /* Pixel colour read by the VGA controller */
+
+ wire [((RESOLUTION == "320x240") ? (16) : (14)):0] user_to_video_memory_addr;
+ /* This bus specifies the address in memory the user must write
+ * data to in order for the pixel intended to appear at location (X,Y) to be displayed
+ * at the correct location on the screen.
+ */
+
+ wire [((RESOLUTION == "320x240") ? (16) : (14)):0] controller_to_video_memory_addr;
+ /* This bus specifies the address in memory the vga controller must read data from
+ * in order to determine the colour of a pixel located at coordinate (X,Y) of the screen.
+ */
+
+ wire clock_25;
+ /* 25MHz clock generated by dividing the input clock frequency by 2. */
+
+ wire vcc, gnd;
+
+ /*****************************************************************************/
+ /* Instances of modules for the VGA adapter. */
+ /*****************************************************************************/
+ assign vcc = 1'b1;
+ assign gnd = 1'b0;
+
+ vga_address_translator user_input_translator(
+ .x(x), .y(y), .mem_address(user_to_video_memory_addr) );
+ defparam user_input_translator.RESOLUTION = RESOLUTION;
+ /* Convert user coordinates into a memory address. */
+
+ assign valid_160x120 = (({1'b0, x} >= 0) & ({1'b0, x} < 160) & ({1'b0, y} >= 0) & ({1'b0, y} < 120)) & (RESOLUTION == "160x120");
+ assign valid_320x240 = (({1'b0, x} >= 0) & ({1'b0, x} < 320) & ({1'b0, y} >= 0) & ({1'b0, y} < 240)) & (RESOLUTION == "320x240");
+ assign writeEn = (plot) & (valid_160x120 | valid_320x240);
+ /* Allow the user to plot a pixel if and only if the (X,Y) coordinates supplied are in a valid range. */
+
+ /* Create video memory. */
+ altsyncram VideoMemory (
+ .wren_a (writeEn),
+ .wren_b (gnd),
+ .clock0 (clock), // write clock
+ .clock1 (clock_25), // read clock
+ .clocken0 (vcc), // write enable clock
+ .clocken1 (vcc), // read enable clock
+ .address_a (user_to_video_memory_addr),
+ .address_b (controller_to_video_memory_addr),
+ .data_a (colour), // data in
+ .q_b (to_ctrl_colour) // data out
+ );
+ defparam
+ VideoMemory.WIDTH_A = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
+ VideoMemory.WIDTH_B = ((MONOCHROME == "FALSE") ? (BITS_PER_COLOUR_CHANNEL*3) : 1),
+ VideoMemory.INTENDED_DEVICE_FAMILY = "Cyclone II",
+ VideoMemory.OPERATION_MODE = "DUAL_PORT",
+ VideoMemory.WIDTHAD_A = ((RESOLUTION == "320x240") ? (17) : (15)),
+ VideoMemory.NUMWORDS_A = ((RESOLUTION == "320x240") ? (76800) : (19200)),
+ VideoMemory.WIDTHAD_B = ((RESOLUTION == "320x240") ? (17) : (15)),
+ VideoMemory.NUMWORDS_B = ((RESOLUTION == "320x240") ? (76800) : (19200)),
+ VideoMemory.OUTDATA_REG_B = "CLOCK1",
+ VideoMemory.ADDRESS_REG_B = "CLOCK1",
+ VideoMemory.CLOCK_ENABLE_INPUT_A = "BYPASS",
+ VideoMemory.CLOCK_ENABLE_INPUT_B = "BYPASS",
+ VideoMemory.CLOCK_ENABLE_OUTPUT_B = "BYPASS",
+ VideoMemory.POWER_UP_UNINITIALIZED = "FALSE",
+ VideoMemory.INIT_FILE = BACKGROUND_IMAGE;
+
+ vga_pll mypll(clock, clock_25);
+ /* This module generates a clock with half the frequency of the input clock.
+ * For the VGA adapter to operate correctly the clock signal 'clock' must be
+ * a 50MHz clock. The derived clock, which will then operate at 25MHz, is
+ * required to set the monitor into the 640x480@60Hz display mode (also known as
+ * the VGA mode).
+ */
+
+ vga_controller controller(
+ .vga_clock(clock_25),
+ .resetn(resetn),
+ .pixel_colour(to_ctrl_colour),
+ .memory_address(controller_to_video_memory_addr),
+ .VGA_R(VGA_R),
+ .VGA_G(VGA_G),
+ .VGA_B(VGA_B),
+ .VGA_HS(VGA_HS),
+ .VGA_VS(VGA_VS),
+ .VGA_BLANK(VGA_BLANK),
+ .VGA_SYNC(VGA_SYNC),
+ .VGA_CLK(VGA_CLK)
+ );
+ defparam controller.BITS_PER_COLOUR_CHANNEL = BITS_PER_COLOUR_CHANNEL ;
+ defparam controller.MONOCHROME = MONOCHROME;
+ defparam controller.RESOLUTION = RESOLUTION;
+ defparam controller.USING_DE1 = USING_DE1;
+
+endmodule
+
\ No newline at end of file diff --git a/vga-core/vga_address_translator.sv b/vga-core/vga_address_translator.sv new file mode 100644 index 0000000..cc63fac --- /dev/null +++ b/vga-core/vga_address_translator.sv @@ -0,0 +1,39 @@ +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +/* This module converts a user specified coordinates into a memory address. + * The output of the module depends on the resolution set by the user. + */ +module vga_address_translator(x, y, mem_address); + + parameter RESOLUTION = "320x240"; + /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on + * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution). + * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary + * to reduce the resolution for the Video Memory to fit within the on-chip memory limits. + */ + + input [((RESOLUTION == "320x240") ? (8) : (7)):0] x; + input [((RESOLUTION == "320x240") ? (7) : (6)):0] y; + output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address; + + /* The basic formula is address = y*WIDTH + x; + * For 320x240 resolution we can write 320 as (256 + 64). Memory address becomes + * (y*256) + (y*64) + x; + * This simplifies multiplication a simple shift and add operation. + * A leading 0 bit is added to each operand to ensure that they are treated as unsigned + * inputs. By default the use a '+' operator will generate a signed adder. + * Similarly, for 160x120 resolution we write 160 as 128+32. + */ + wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x}); + wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x}); + + always @(*) + begin + if (RESOLUTION == "320x240") + mem_address = res_320x240; + else + mem_address = res_160x120[14:0]; + end +endmodule diff --git a/vga-core/vga_address_translator.v b/vga-core/vga_address_translator.v new file mode 100644 index 0000000..bf97e90 --- /dev/null +++ b/vga-core/vga_address_translator.v @@ -0,0 +1,35 @@ +/* This module converts a user specified coordinates into a memory address.
+ * The output of the module depends on the resolution set by the user.
+ */
+module vga_address_translator(x, y, mem_address);
+
+ parameter RESOLUTION = "320x240";
+ /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
+ * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
+ * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
+ * to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
+ */
+
+ input [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
+ input [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
+ output reg [((RESOLUTION == "320x240") ? (16) : (14)):0] mem_address;
+
+ /* The basic formula is address = y*WIDTH + x;
+ * For 320x240 resolution we can write 320 as (256 + 64). Memory address becomes
+ * (y*256) + (y*64) + x;
+ * This simplifies multiplication a simple shift and add operation.
+ * A leading 0 bit is added to each operand to ensure that they are treated as unsigned
+ * inputs. By default the use a '+' operator will generate a signed adder.
+ * Similarly, for 160x120 resolution we write 160 as 128+32.
+ */
+ wire [16:0] res_320x240 = ({1'b0, y, 8'd0} + {1'b0, y, 6'd0} + {1'b0, x});
+ wire [15:0] res_160x120 = ({1'b0, y, 7'd0} + {1'b0, y, 5'd0} + {1'b0, x});
+
+ always @(*)
+ begin
+ if (RESOLUTION == "320x240")
+ mem_address = res_320x240;
+ else
+ mem_address = res_160x120[14:0];
+ end
+endmodule
diff --git a/vga-core/vga_controller.sv b/vga-core/vga_controller.sv new file mode 100644 index 0000000..4217c13 --- /dev/null +++ b/vga-core/vga_controller.sv @@ -0,0 +1,216 @@ +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input. + * + * General approach: + * Go through each line of the screen and read the colour each pixel on that line should have from + * the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to + * a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is + * read from video memory its brightness is first increased before it is forwarded to the VGA DAC. + */ +module vga_controller( vga_clock, resetn, pixel_colour, memory_address, + VGA_R, VGA_G, VGA_B, + VGA_HS, VGA_VS, VGA_BLANK, + VGA_SYNC, VGA_CLK); + + /* Screen resolution and colour depth parameters. */ + + parameter BITS_PER_COLOUR_CHANNEL = 1; + /* The number of bits per colour channel used to represent the colour of each pixel. A value + * of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity + * of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours. + * In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is + * limited by the screen resolution and the amount of on-chip memory available on the target device. + */ + + parameter MONOCHROME = "FALSE"; + /* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce + * the amount of memory you will use by a factor of 3. */ + + parameter RESOLUTION = "320x240"; + /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on + * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution). + * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary + * to reduce the resolution for the Video Memory to fit within the on-chip memory limits. + */ + + parameter USING_DE1 = "FALSE"; + /* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences + * between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if + * you are running your circuit on a DE1 board. */ + + //--- Timing parameters. + /* Recall that the VGA specification requires a few more rows and columns are drawn + * when refreshing the screen than are actually present on the screen. This is necessary to + * generate the vertical and the horizontal syncronization signals. If you wish to use a + * display mode other than 640x480 you will need to modify the parameters below as well + * as change the frequency of the clock driving the monitor (VGA_CLK). + */ + parameter C_VERT_NUM_PIXELS = 11'd480; + parameter C_VERT_SYNC_START = 11'd493; + parameter C_VERT_SYNC_END = 11'd494; //(C_VERT_SYNC_START + 2 - 1); + parameter C_VERT_TOTAL_COUNT = 11'd525; + + parameter C_HORZ_NUM_PIXELS = 11'd640; + parameter C_HORZ_SYNC_START = 11'd659; + parameter C_HORZ_SYNC_END = 11'd754; //(C_HORZ_SYNC_START + 96 - 1); + parameter C_HORZ_TOTAL_COUNT = 11'd800; + + /*****************************************************************************/ + /* Declare inputs and outputs. */ + /*****************************************************************************/ + + input vga_clock, resetn; + input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour; + output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address; + output reg [9:0] VGA_R; + output reg [9:0] VGA_G; + output reg [9:0] VGA_B; + output reg VGA_HS; + output reg VGA_VS; + output reg VGA_BLANK; + output VGA_SYNC, VGA_CLK; + + /*****************************************************************************/ + /* Local Signals. */ + /*****************************************************************************/ + + reg VGA_HS1; + reg VGA_VS1; + reg VGA_BLANK1; + reg [9:0] xCounter, yCounter; + wire xCounter_clear; + wire yCounter_clear; + wire vcc; + + reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x; + reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y; + /* Inputs to the converter. */ + + /*****************************************************************************/ + /* Controller implementation. */ + /*****************************************************************************/ + + assign vcc =1'b1; + + /* A counter to scan through a horizontal line. */ + always @(posedge vga_clock or negedge resetn) + begin + if (!resetn) + xCounter <= 10'd0; + else if (xCounter_clear) + xCounter <= 10'd0; + else + begin + xCounter <= xCounter + 1'b1; + end + end + assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1)); + + /* A counter to scan vertically, indicating the row currently being drawn. */ + always @(posedge vga_clock or negedge resetn) + begin + if (!resetn) + yCounter <= 10'd0; + else if (xCounter_clear && yCounter_clear) + yCounter <= 10'd0; + else if (xCounter_clear) //Increment when x counter resets + yCounter <= yCounter + 1'b1; + end + assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1)); + + /* Convert the xCounter/yCounter location from screen pixels (640x480) to our + * local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4, + * depending on the resolution. */ + always @(*) + begin + if (RESOLUTION == "320x240") + begin + x = xCounter[9:1]; + y = yCounter[8:1]; + end + else + begin + x = xCounter[9:2]; + y = yCounter[8:2]; + end + end + + /* Change the (x,y) coordinate into a memory address. */ + vga_address_translator controller_translator( + .x(x), .y(y), .mem_address(memory_address) ); + defparam controller_translator.RESOLUTION = RESOLUTION; + + + /* Generate the vertical and horizontal synchronization pulses. */ + always @(posedge vga_clock) + begin + //- Sync Generator (ACTIVE LOW) + if (USING_DE1 == "TRUE") + VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START-2) && (xCounter <= C_HORZ_SYNC_END-2)); + else + VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END)); + VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END)); + + //- Current X and Y is valid pixel range + VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS)); + + //- Add 1 cycle delay + VGA_HS <= VGA_HS1; + VGA_VS <= VGA_VS1; + VGA_BLANK <= VGA_BLANK1; + end + + /* VGA sync should be 1 at all times. */ + assign VGA_SYNC = vcc; + + /* Generate the VGA clock signal. */ + assign VGA_CLK = vga_clock; + + /* Brighten the colour output. */ + // The colour input is first processed to brighten the image a little. Setting the top + // bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image, + // each bit of the colour is replicated through the 10 DAC colour input bits. For example, + // when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the + // VGA_R input to the DAC will be set to 10'b1010101010. + + integer index; + integer sub_index; + + wire on_screen; + + assign on_screen = (USING_DE1 == "TRUE") ? + (({1'b0, xCounter} >= 2) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS)) : + (({1'b0, xCounter} >= 0) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS)); + + always @(pixel_colour or on_screen) + begin + VGA_R <= 'b0; + VGA_G <= 'b0; + VGA_B <= 'b0; + if (MONOCHROME == "FALSE") + begin + for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL) + begin + for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1) + begin + VGA_R[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2]; + VGA_G[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL]; + VGA_B[sub_index+index] <= on_screen & pixel_colour[sub_index]; + end + end + end + else + begin + for (index = 0; index < 10; index = index + 1) + begin + VGA_R[index] <= on_screen & pixel_colour[0:0]; + VGA_G[index] <= on_screen & pixel_colour[0:0]; + VGA_B[index] <= on_screen & pixel_colour[0:0]; + end + end + end + +endmodule diff --git a/vga-core/vga_controller.v b/vga-core/vga_controller.v new file mode 100644 index 0000000..0e4cfba --- /dev/null +++ b/vga-core/vga_controller.v @@ -0,0 +1,212 @@ +/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
+ *
+ * General approach:
+ * Go through each line of the screen and read the colour each pixel on that line should have from
+ * the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
+ * a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
+ * read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
+ */
+module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
+ VGA_R, VGA_G, VGA_B,
+ VGA_HS, VGA_VS, VGA_BLANK,
+ VGA_SYNC, VGA_CLK);
+
+ /* Screen resolution and colour depth parameters. */
+
+ parameter BITS_PER_COLOUR_CHANNEL = 1;
+ /* The number of bits per colour channel used to represent the colour of each pixel. A value
+ * of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
+ * of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
+ * In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is
+ * limited by the screen resolution and the amount of on-chip memory available on the target device.
+ */
+
+ parameter MONOCHROME = "FALSE";
+ /* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
+ * the amount of memory you will use by a factor of 3. */
+
+ parameter RESOLUTION = "320x240";
+ /* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
+ * the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
+ * It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
+ * to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
+ */
+
+ parameter USING_DE1 = "FALSE";
+ /* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
+ * between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
+ * you are running your circuit on a DE1 board. */
+
+ //--- Timing parameters.
+ /* Recall that the VGA specification requires a few more rows and columns are drawn
+ * when refreshing the screen than are actually present on the screen. This is necessary to
+ * generate the vertical and the horizontal syncronization signals. If you wish to use a
+ * display mode other than 640x480 you will need to modify the parameters below as well
+ * as change the frequency of the clock driving the monitor (VGA_CLK).
+ */
+ parameter C_VERT_NUM_PIXELS = 11'd480;
+ parameter C_VERT_SYNC_START = 11'd493;
+ parameter C_VERT_SYNC_END = 11'd494; //(C_VERT_SYNC_START + 2 - 1);
+ parameter C_VERT_TOTAL_COUNT = 11'd525;
+
+ parameter C_HORZ_NUM_PIXELS = 11'd640;
+ parameter C_HORZ_SYNC_START = 11'd659;
+ parameter C_HORZ_SYNC_END = 11'd754; //(C_HORZ_SYNC_START + 96 - 1);
+ parameter C_HORZ_TOTAL_COUNT = 11'd800;
+
+ /*****************************************************************************/
+ /* Declare inputs and outputs. */
+ /*****************************************************************************/
+
+ input vga_clock, resetn;
+ input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
+ output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
+ output reg [9:0] VGA_R;
+ output reg [9:0] VGA_G;
+ output reg [9:0] VGA_B;
+ output reg VGA_HS;
+ output reg VGA_VS;
+ output reg VGA_BLANK;
+ output VGA_SYNC, VGA_CLK;
+
+ /*****************************************************************************/
+ /* Local Signals. */
+ /*****************************************************************************/
+
+ reg VGA_HS1;
+ reg VGA_VS1;
+ reg VGA_BLANK1;
+ reg [9:0] xCounter, yCounter;
+ wire xCounter_clear;
+ wire yCounter_clear;
+ wire vcc;
+
+ reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
+ reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
+ /* Inputs to the converter. */
+
+ /*****************************************************************************/
+ /* Controller implementation. */
+ /*****************************************************************************/
+
+ assign vcc =1'b1;
+
+ /* A counter to scan through a horizontal line. */
+ always @(posedge vga_clock or negedge resetn)
+ begin
+ if (!resetn)
+ xCounter <= 10'd0;
+ else if (xCounter_clear)
+ xCounter <= 10'd0;
+ else
+ begin
+ xCounter <= xCounter + 1'b1;
+ end
+ end
+ assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
+
+ /* A counter to scan vertically, indicating the row currently being drawn. */
+ always @(posedge vga_clock or negedge resetn)
+ begin
+ if (!resetn)
+ yCounter <= 10'd0;
+ else if (xCounter_clear && yCounter_clear)
+ yCounter <= 10'd0;
+ else if (xCounter_clear) //Increment when x counter resets
+ yCounter <= yCounter + 1'b1;
+ end
+ assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
+
+ /* Convert the xCounter/yCounter location from screen pixels (640x480) to our
+ * local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4,
+ * depending on the resolution. */
+ always @(*)
+ begin
+ if (RESOLUTION == "320x240")
+ begin
+ x = xCounter[9:1];
+ y = yCounter[8:1];
+ end
+ else
+ begin
+ x = xCounter[9:2];
+ y = yCounter[8:2];
+ end
+ end
+
+ /* Change the (x,y) coordinate into a memory address. */
+ vga_address_translator controller_translator(
+ .x(x), .y(y), .mem_address(memory_address) );
+ defparam controller_translator.RESOLUTION = RESOLUTION;
+
+
+ /* Generate the vertical and horizontal synchronization pulses. */
+ always @(posedge vga_clock)
+ begin
+ //- Sync Generator (ACTIVE LOW)
+ if (USING_DE1 == "TRUE")
+ VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START-2) && (xCounter <= C_HORZ_SYNC_END-2));
+ else
+ VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
+ VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
+
+ //- Current X and Y is valid pixel range
+ VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
+
+ //- Add 1 cycle delay
+ VGA_HS <= VGA_HS1;
+ VGA_VS <= VGA_VS1;
+ VGA_BLANK <= VGA_BLANK1;
+ end
+
+ /* VGA sync should be 1 at all times. */
+ assign VGA_SYNC = vcc;
+
+ /* Generate the VGA clock signal. */
+ assign VGA_CLK = vga_clock;
+
+ /* Brighten the colour output. */
+ // The colour input is first processed to brighten the image a little. Setting the top
+ // bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image,
+ // each bit of the colour is replicated through the 10 DAC colour input bits. For example,
+ // when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the
+ // VGA_R input to the DAC will be set to 10'b1010101010.
+
+ integer index;
+ integer sub_index;
+
+ wire on_screen;
+
+ assign on_screen = (USING_DE1 == "TRUE") ?
+ (({1'b0, xCounter} >= 2) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS)) :
+ (({1'b0, xCounter} >= 0) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS));
+
+ always @(pixel_colour or on_screen)
+ begin
+ VGA_R <= 'b0;
+ VGA_G <= 'b0;
+ VGA_B <= 'b0;
+ if (MONOCHROME == "FALSE")
+ begin
+ for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
+ begin
+ for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
+ begin
+ VGA_R[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
+ VGA_G[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
+ VGA_B[sub_index+index] <= on_screen & pixel_colour[sub_index];
+ end
+ end
+ end
+ else
+ begin
+ for (index = 0; index < 10; index = index + 1)
+ begin
+ VGA_R[index] <= on_screen & pixel_colour[0:0];
+ VGA_G[index] <= on_screen & pixel_colour[0:0];
+ VGA_B[index] <= on_screen & pixel_colour[0:0];
+ end
+ end
+ end
+
+endmodule
diff --git a/vga-core/vga_pll.sv b/vga-core/vga_pll.sv new file mode 100644 index 0000000..d433ef5 --- /dev/null +++ b/vga-core/vga_pll.sv @@ -0,0 +1,173 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: VgaPll.v +// Megafunction Name(s): +// altpll +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2005 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module vga_pll ( + clock_in, + clock_out); + + input clock_in; + output clock_out; + + wire [5:0] clock_output_bus; + wire [1:0] clock_input_bus; + wire gnd; + + assign gnd = 1'b0; + assign clock_input_bus = { gnd, clock_in }; + + altpll altpll_component ( + .inclk (clock_input_bus), + .clk (clock_output_bus) + ); + defparam + altpll_component.operation_mode = "NORMAL", + altpll_component.intended_device_family = "Cyclone II", + altpll_component.lpm_type = "altpll", + altpll_component.pll_type = "FAST", + /* Specify the input clock to be a 50MHz clock. A 50 MHz clock is present + * on PIN_N2 on the DE2 board. We need to specify the input clock frequency + * in order to set up the PLL correctly. To do this we must put the input clock + * period measured in picoseconds in the inclk0_input_frequency parameter. + * 1/(20000 ps) = 0.5 * 10^(5) Hz = 50 * 10^(6) Hz = 50 MHz. */ + altpll_component.inclk0_input_frequency = 20000, + altpll_component.primary_clock = "INCLK0", + /* Specify output clock parameters. The output clock should have a + * frequency of 25 MHz, with 50% duty cycle. */ + altpll_component.compensate_clock = "CLK0", + altpll_component.clk0_phase_shift = "0", + altpll_component.clk0_divide_by = 2, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_duty_cycle = 50; + + assign clock_out = clock_output_bus[0]; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.bsf FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_bb.v FALSE FALSE diff --git a/vga-core/vga_pll.v b/vga-core/vga_pll.v new file mode 100644 index 0000000..bbf375f --- /dev/null +++ b/vga-core/vga_pll.v @@ -0,0 +1,173 @@ +// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: VgaPll.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module vga_pll (
+ clock_in,
+ clock_out);
+
+ input clock_in;
+ output clock_out;
+
+ wire [5:0] clock_output_bus;
+ wire [1:0] clock_input_bus;
+ wire gnd;
+
+ assign gnd = 1'b0;
+ assign clock_input_bus = { gnd, clock_in };
+
+ altpll altpll_component (
+ .inclk (clock_input_bus),
+ .clk (clock_output_bus)
+ );
+ defparam
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.pll_type = "FAST",
+ /* Specify the input clock to be a 50MHz clock. A 50 MHz clock is present
+ * on PIN_N2 on the DE2 board. We need to specify the input clock frequency
+ * in order to set up the PLL correctly. To do this we must put the input clock
+ * period measured in picoseconds in the inclk0_input_frequency parameter.
+ * 1/(20000 ps) = 0.5 * 10^(5) Hz = 50 * 10^(6) Hz = 50 MHz. */
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.primary_clock = "INCLK0",
+ /* Specify output clock parameters. The output clock should have a
+ * frequency of 25 MHz, with 50% duty cycle. */
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk0_divide_by = 2,
+ altpll_component.clk0_multiply_by = 1,
+ altpll_component.clk0_duty_cycle = 50;
+
+ assign clock_out = clock_output_bus[0];
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_bb.v FALSE FALSE
diff --git a/vga-hacks/vga_adapter_sim.sv b/vga-hacks/vga_adapter_sim.sv new file mode 100644 index 0000000..1fb0142 --- /dev/null +++ b/vga-hacks/vga_adapter_sim.sv @@ -0,0 +1,22 @@ +// For simulation only + +module vga_adapter(input logic resetn, input logic clock, input logic [2:0] colour, + input logic [7:0] x, input logic [6:0] y, input logic plot, + output logic [9:0] VGA_R, output logic [9:0] VGA_G, output logic [9:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_BLANK, + output logic VGA_SYNC, output logic VGA_CLK); + parameter BITS_PER_COLOUR_CHANNEL = 1; + parameter MONOCHROME = "FALSE"; + parameter RESOLUTION = "320x240"; + parameter BACKGROUND_IMAGE = "background.mif"; + parameter USING_DE1 = "FALSE"; + + always_ff @(posedge clock, negedge resetn) begin + if (~resetn) begin + $display("VGA: reset"); + end else if (plot) begin + $display("VGA: plot (%d,%d) colour %03b", x, y, colour); + end + end +endmodule: vga_adapter + diff --git a/vga-hacks/vga_adapter_window.sv b/vga-hacks/vga_adapter_window.sv new file mode 100644 index 0000000..278903c --- /dev/null +++ b/vga-hacks/vga_adapter_window.sv @@ -0,0 +1,24 @@ +// For simulation only + +module vga_adapter(input logic resetn, input logic clock, input logic [2:0] colour, + input logic [7:0] x, input logic [6:0] y, input logic plot, + output logic [9:0] VGA_R, output logic [9:0] VGA_G, output logic [9:0] VGA_B, + output logic VGA_HS, output logic VGA_VS, output logic VGA_BLANK, + output logic VGA_SYNC, output logic VGA_CLK); + parameter BITS_PER_COLOUR_CHANNEL = 1; + parameter MONOCHROME = "FALSE"; + parameter RESOLUTION = "320x240"; + parameter BACKGROUND_IMAGE = "background.mif"; + parameter USING_DE1 = "FALSE"; + + always_ff @(posedge clock, negedge resetn) begin + if (!resetn) begin + void'(mti_fli::mti_Cmd("vga::reset")); + end else if (plot) begin + if ((^x === 1'bx) || (^y === 1'bx) || (^colour === 1'bx)) + $error("cannot plot undefined values"); + else + void'(mti_fli::mti_Cmd($sformatf("vga::plot %d %d %d", x, y, colour))); + end + end +endmodule: vga_adapter diff --git a/vga-hacks/vga_window.tcl b/vga-hacks/vga_window.tcl new file mode 100644 index 0000000..5ad7aaf --- /dev/null +++ b/vga-hacks/vga_window.tcl @@ -0,0 +1,85 @@ +namespace eval vga { + set zoom 4 + set width 160 + set height 120 + set bg "#808080" + set count 0 +} + +proc vga::init {} { + toplevel .vga -padx 5 -pady 5 + wm title .vga "fake VGA screen" + + frame .vga.draw + pack .vga.draw -expand 1 -fill both + + frame .vga.status + button .vga.status.reset -width 5 -relief ridge -text "reset" -command { vga::reset } + label .vga.status.count_legend -text " count:" + label .vga.status.count_val -relief groove -width 10 + + label .vga.status.drawn_legend -text "last:" + label .vga.status.drawn_pos -relief groove -width 7 + label .vga.status.click_legend -text " clicked:" + label .vga.status.click_pos -relief groove -width 7 + label .vga.status.mouse_legend -text " mouse:" + label .vga.status.mouse_pos -relief groove -width 7 + pack .vga.status.reset .vga.status.count_legend .vga.status.count_val -side left + pack .vga.status.mouse_pos .vga.status.mouse_legend .vga.status.click_pos .vga.status.click_legend \ + .vga.status.drawn_pos .vga.status.drawn_legend -side right + pack .vga.status -side bottom -fill x + .vga.status.drawn_pos configure -text "-,-" + .vga.status.mouse_pos configure -text "-,-" + .vga.status.click_pos configure -text "-,-" + + set w [expr $vga::width * $vga::zoom] + set h [expr {$vga::height * $vga::zoom}] + canvas .vga.draw.c -width $w -height $h -bg $vga::bg + pack .vga.draw.c -expand 1 -fill both + bind .vga.draw.c <Motion> { vga::show_mouse %x %y } + bind .vga.draw.c <ButtonPress> { vga::show_click %x %y } + bind .vga.draw.c <Leave> { .vga.status.mouse_pos configure -text "-,-" } +} + +proc vga::reset {} { + .vga.draw.c create rectangle 0 0 [expr $vga::width * $vga::zoom - 1] [expr $vga::height * $vga::zoom - 1] -outline $vga::bg -fill $vga::bg + set vga::count 0 + .vga.status.count_val configure -text "$vga::count" + .vga.status.drawn_pos configure -text "-,-" +} + +proc vga::rgb_to_hex {c} { + set b [expr ($c & 1) * 255] + set g [expr (($c >> 1) & 1) * 255] + set r [expr (($c >> 2) & 1) * 255] + return [format "#%02x%02x%02x" $r $g $b] +} + +proc vga::plot {x y c} { + if {[expr $x < 0]} { return } + if {[expr $x >= $vga::width]} { return } + if {[expr $y < 0]} { return } + if {[expr $y >= $vga::height]} { return } + if !({[winfo exists .vga]}) {vga::init} + set x0 [expr $x * $vga::zoom] + set y0 [expr $y * $vga::zoom] + set x1 [expr ($x+1) * $vga::zoom - 1] + set y1 [expr ($y+1) * $vga::zoom - 1] + set clr [vga::rgb_to_hex $c] + .vga.draw.c create rectangle $x0 $y0 $x1 $y1 -outline $clr -fill $clr + incr vga::count + .vga.status.count_val configure -text "$vga::count" + .vga.status.drawn_pos configure -text "$x,$y:$c" +} + +proc vga::show_mouse {x0 y0} { + set x [expr $x0 / $vga::zoom] + set y [expr $y0 / $vga::zoom] + .vga.status.mouse_pos configure -text "$x,$y" +} + +proc vga::show_click {x0 y0} { + set x [expr $x0 / $vga::zoom] + set y [expr $y0 / $vga::zoom] + .vga.status.click_pos configure -text "$x,$y" +} |
