aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--task3/circle.sv40
-rw-r--r--task3/task3.sv50
-rw-r--r--task4/reuleaux.sv36
-rw-r--r--task4/task4.sv51
4 files changed, 84 insertions, 93 deletions
diff --git a/task3/circle.sv b/task3/circle.sv
index c6218d8..c8dd60d 100644
--- a/task3/circle.sv
+++ b/task3/circle.sv
@@ -14,14 +14,14 @@ module circle(clk, rst_n, colour, centre_x, centre_y, radius, start, done,
output logic [6:0] vga_y;
output logic [7:0] vga_x;
- logic clear, ready;
+ logic clear;
logic [2:0] octant;
logic [7:0] offset_x, offset_y, offset_x_next, offset_y_next;
/* One bit larger since these are signed. */
logic signed [7:0] vga_y_next;
logic signed [8:0] vga_x_next, crit, crit_next;
- assign vga_colour = clear ? 3'b000 : colour;
+ assign vga_colour = colour;
always_comb case (octant)
3'd0: begin
@@ -72,44 +72,21 @@ module circle(clk, rst_n, colour, centre_x, centre_y, radius, start, done,
end
always_ff @(posedge clk) begin
- if (~rst_n) begin
+ if (rst_n !== 1) begin
done <= 1'b0;
- ready <= 1'b0;
- /* Start clearing the screen. */
- clear <= 1'b1;
+ /* Initialise the registers for the circle algorithm. */
vga_x <= 8'b0;
vga_y <= 7'b0;
- vga_plot <= 1'b1;
- end
-
- /* Clear the screen. */
- if (clear) begin
- if (vga_y < 120) begin
- /* Check for one column less since it takes
- * one clock cycle to reset and increment. */
- if (vga_x < 159)
- vga_x <= vga_x + 1;
- else begin
- vga_x <= 8'b0;
- vga_y <= vga_y + 1;
- end
- end else begin
- clear <= 1'b0;
- ready <= 1'b1;
- vga_x <= 8'b0;
- vga_y <= 7'b0;
- vga_plot <= 1'b0;
- end
- /* Initialise the registers for the circle algorithm. */
- end else if (ready && start && ~done) begin
- ready <= 1'b0;
+ vga_plot <= 1'b0;
octant <= 3'b0;
offset_y <= 8'b0;
offset_x <= radius;
crit <= 1 - radius;
+ end
+
/* Draw the circle using the Bresenham circle algorithm. */
- end else if (start && ~done) begin
+ if (start && ~done) begin
if (offset_y <= offset_x) begin
if ((vga_x_next >= 0) && (vga_x_next <= `VGA_W))
vga_x <= vga_x_next;
@@ -133,7 +110,6 @@ module circle(clk, rst_n, colour, centre_x, centre_y, radius, start, done,
/* Finished. */
end else begin
done <= 1'b1;
- ready <= 1'b1;
vga_plot <= 1'b0;
end
/* Wait for start to be deasserted. */
diff --git a/task3/task3.sv b/task3/task3.sv
index ddb4e9a..c40f464 100644
--- a/task3/task3.sv
+++ b/task3/task3.sv
@@ -11,26 +11,46 @@ module task3(CLOCK_50, KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
output logic [7:0] VGA_X, VGA_R, VGA_G, VGA_B;
output logic [9:0] LEDR;
- logic resetn, start, done;
- logic [2:0] colour;
- logic [6:0] center_y;
- logic [7:0] center_x, radius;
-
- assign resetn = KEY[3];
- assign start = ~KEY[0];
- assign colour = 3'b010;
- assign LEDR[0] = done;
-
- assign center_x = 8'd80;
- assign center_y = 7'd60;
- assign radius = SW[7:0];
+ logic resetn, done, fillscreen_start, circle_start,
+ fillscreen_done, circle_done, fillscreen_plot, circle_plot;
+ logic [2:0] fillscreen_colour, circle_colour;
+ logic [6:0] fillscreen_y, circle_y;
+ logic [7:0] fillscreen_x, circle_x;
vga_adapter #(.RESOLUTION("160x120")) U0(resetn, CLOCK_50,
VGA_COLOUR, VGA_X, VGA_Y, VGA_PLOT,
{VGA_R, 2'b00}, {VGA_G, 2'b00}, {VGA_B, 2'b00},
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK);
- circle U1(CLOCK_50, resetn, colour, center_x, center_y, radius,
- start, done, VGA_X, VGA_Y, VGA_COLOUR, VGA_PLOT);
+ fillscreen U1(CLOCK_50, resetn, 3'b000, fillscreen_start,
+ fillscreen_done, fillscreen_vga_x, fillscreen_vga_y,
+ fillscreen_colour, fillscreen_plot);
+
+ circle U2(CLOCK_50, resetn, 3'b010, 8'd80, 7'd60, 8'd40,
+ circle_start, circle_done, circle_x, circle_y,
+ circle_colour, circle_plot);
+
+ assign resetn = KEY[3];
+ assign start = ~KEY[0];
+ assign LEDR[0] = done;
+
+ assign VGA_X = fillscreen_start ? fillscreen_vga_x : circle_x;
+ assign VGA_Y = fillscreen_start ? fillscreen_vga_y : circle_y;
+ assign VGA_COLOUR = fillscreen_start ? fillscreen_colour : circle_colour;
+ assign VGA_PLOT = fillscreen_start ? fillscreen_plot : circle_plot;
+
+ always_ff @(posedge CLOCK_50) begin
+ if (~resetn) begin
+ fillscreen_start <= 1'b0;
+ circle_start <= 1'b1;
+ done <= 1'b0;
+ end else if (fillscreen_done) begin
+ fillscreen_start <= 1'b0;
+ circle_start <= 1'b1;
+ end else if (circle_done) begin
+ circle_start <= 1'b0;
+ done <= 1'b1;
+ end
+ end
endmodule: task3
diff --git a/task4/reuleaux.sv b/task4/reuleaux.sv
index cc89f4f..e518b63 100644
--- a/task4/reuleaux.sv
+++ b/task4/reuleaux.sv
@@ -14,7 +14,7 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
output logic [6:0] vga_y;
output logic [7:0] vga_x;
- logic clear, ready, vga_plot_next;
+ logic clear, vga_plot_next;
logic [2:0] octant;
/* Auxiliary value for calculations. 21-bit number since we multiply
* 8-bit and 13-bit numbers together. */
@@ -114,42 +114,19 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
always_ff @(posedge clk) begin
if (~rst_n) begin
done <= 1'b0;
- ready <= 1'b0;
- /* Start clearing the screen. */
- clear <= 1'b1;
+ /* Initialise the registers for the circle algorithm. */
vga_x <= 8'b0;
vga_y <= 7'b0;
- vga_plot <= 1'b1;
- end
-
- /* Clear the screen. */
- if (clear) begin
- if (vga_y < 120) begin
- /* Check for one column less since it takes
- * one clock cycle to reset and increment. */
- if (vga_x < 159)
- vga_x <= vga_x + 1;
- else begin
- vga_x <= 8'b0;
- vga_y <= vga_y + 1;
- end
- end else begin
- clear <= 1'b0;
- ready <= 1'b1;
- vga_x <= 8'b0;
- vga_y <= 7'b0;
- vga_plot <= 1'b0;
- end
- /* Initialise the registers for the circle algorithm. */
- end else if (ready && start && ~done) begin
- ready <= 1'b0;
+ vga_plot <= 1'b0;
octant <= 3'b0;
offset_y <= 9'b0;
offset_x <= radius;
crit <= 1 - radius;
+ end
+
/* Draw the circle using the Bresenham circle algorithm. */
- end else if (start && ~done) begin
+ if (start && ~done) begin
if (offset_y <= offset_x) begin
if ((vga_x_next >= 0) && (vga_x_next <= `VGA_W))
vga_x <= vga_x_next;
@@ -174,7 +151,6 @@ module reuleaux(clk, rst_n, colour, centre_x, centre_y, diameter, start, done,
/* Finished. */
end else begin
done <= 1'b1;
- ready <= 1'b1;
vga_plot <= 1'b0;
end
/* Wait for start to be deasserted. */
diff --git a/task4/task4.sv b/task4/task4.sv
index 1426a72..80d278b 100644
--- a/task4/task4.sv
+++ b/task4/task4.sv
@@ -11,27 +11,46 @@ module task4(CLOCK_50, KEY, SW, LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
output logic [7:0] VGA_X, VGA_R, VGA_G, VGA_B;
output logic [9:0] LEDR;
- logic resetn, start, done;
- logic [2:0] colour;
- logic [6:0] center_y;
- logic [7:0] center_x, diameter;
-
- assign resetn = KEY[3];
- assign start = ~KEY[0];
- assign colour = 3'b010;
- assign LEDR[0] = done;
-
- assign center_x = 8'd80;
- assign center_y = 7'd60;
- assign diameter = SW[7:0];
+ logic resetn, done, fillscreen_start, reuleaux_start,
+ fillscreen_done, reuleaux_done, fillscreen_plot, reuleaux_plot;
+ logic [2:0] fillscreen_colour, reuleaux_colour;
+ logic [6:0] fillscreen_y, reuleaux_y;
+ logic [7:0] fillscreen_x, reuleaux_x;
vga_adapter #(.RESOLUTION("160x120")) U0(resetn, CLOCK_50,
VGA_COLOUR, VGA_X, VGA_Y, VGA_PLOT,
{VGA_R, 2'b00}, {VGA_G, 2'b00}, {VGA_B, 2'b00},
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK);
- reuleaux U1(CLOCK_50, resetn, colour, center_x, center_y, diameter,
- start, done, VGA_X, VGA_Y, VGA_COLOUR, VGA_PLOT);
+ fillscreen U1(CLOCK_50, resetn, 3'b000, fillscreen_start,
+ fillscreen_done, fillscreen_vga_x, fillscreen_vga_y,
+ fillscreen_colour, fillscreen_plot);
-endmodule: task4
+ reuleaux U2(CLOCK_50, resetn, 3'b010, 8'd80, 7'd60, 8'd80,
+ reuleaux_start, reuleaux_done, reuleaux_x, reuleaux_y,
+ reuleaux_colour, reuleaux_plot);
+ assign resetn = KEY[3];
+ assign start = ~KEY[0];
+ assign LEDR[0] = done;
+
+ assign VGA_X = fillscreen_start ? fillscreen_vga_x : reuleaux_x;
+ assign VGA_Y = fillscreen_start ? fillscreen_vga_y : reuleaux_y;
+ assign VGA_COLOUR = fillscreen_start ? fillscreen_colour : reuleaux_colour;
+ assign VGA_PLOT = fillscreen_start ? fillscreen_plot : reuleaux_plot;
+
+ always_ff @(posedge CLOCK_50) begin
+ if (~resetn) begin
+ fillscreen_start <= 1'b0;
+ reuleaux_start <= 1'b1;
+ done <= 1'b0;
+ end else if (fillscreen_done) begin
+ fillscreen_start <= 1'b0;
+ reuleaux_start <= 1'b1;
+ end else if (reuleaux_done) begin
+ reuleaux_start <= 1'b0;
+ done <= 1'b1;
+ end
+ end
+
+endmodule: task4
generated by cgit v1.2.3 (git 2.39.1) at 2026-03-12 22:56:51 +0000