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| author | Warrick Lo <wlo@warricklo.net> | 2026-06-14 18:18:32 -0700 |
|---|---|---|
| committer | Warrick Lo <wlo@warricklo.net> | 2026-06-14 18:18:32 -0700 |
| commit | eef204455c692cee60e3713bad6c7428627b3672 (patch) | |
| tree | f08ace03d14fe11759193badef3fbad4dfdc1662 /rtl/rv32e_core_wrapper.sv | |
| parent | Add top-level and QSPI controller modules (diff) | |
| download | montreal-eef204455c692cee60e3713bad6c7428627b3672.tar.xz montreal-eef204455c692cee60e3713bad6c7428627b3672.zip | |
Rename top-level module to prevent clashes
Also fixes linter errors, whitespace, and copyright.
Top-level module name MUST be unique to avoid collisions with other
projects in the shuttle run.
The port list MUST also exactly follow the Tiny Tapeout template, so a
comment has been added to emphasise this.
Signed-off-by: Warrick Lo <wlo@warricklo.net>
Diffstat (limited to 'rtl/rv32e_core_wrapper.sv')
| -rw-r--r-- | rtl/rv32e_core_wrapper.sv | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/rtl/rv32e_core_wrapper.sv b/rtl/rv32e_core_wrapper.sv index 8d2b5c9..773b7af 100644 --- a/rtl/rv32e_core_wrapper.sv +++ b/rtl/rv32e_core_wrapper.sv @@ -1,8 +1,16 @@ -// Provides a clean, generic bus interface for the core -// Easier UVM access - -module rv32e_core_wrapper (); +/* SPDX-License-Identifier: CERN-OHL-P-2.0 */ +/* + * Copyright 2026 UBC ASIC contributors (Montreal project). + * All rights reserved. + * + * Authors: Chathil Rajamanthree <chathil.rajaman3@gmail.com> + * + * Montreal RV32E Core Wrapper + * + * Provides a clean, generic bus interface for the core for easier UVM access. + */ +module rv32e_core_wrapper (); -endmodule +endmodule : rv32e_core_wrapper |