Initial commit

3 files changed, 32 insertions, 0 deletions

diff --git a/task1/.gitignore b/task1/.gitignore
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+++ b/task1/.gitignore
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+.DS_Store
+transcript
+tcl_stacktrace.txt
+c5_pin_model_dump.txt
+*.mti
+*.mpf
+*.wlf
+*.qdb
+*.qpg
+*.qtl
+*.qpf
+*.sof
+*.bak
+work/
+db/
+incremental_db/
+simulation/
+output_files/
diff --git a/task1/card7seg.sv b/task1/card7seg.sv
new file mode 100644
index 0000000..b994e3e
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+++ b/task1/card7seg.sv
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+module card7seg(input logic [3:0] SW, output logic [6:0] HEX0);
+		
+   // your code goes here
+	
+endmodule
+
diff --git a/task1/tb_card7seg.sv b/task1/tb_card7seg.sv
new file mode 100644
index 0000000..3a985c9
--- /dev/null
+++ b/task1/tb_card7seg.sv
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+module tb_card7seg();
+
+// Your testbench goes here. Make sure your tests exercise the entire design
+// in the .sv file.  Note that in our tests the simulator will exit after
+// 10,000 ticks (equivalent to "initial #10000 $finish();").
+						
+endmodule
+