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diff --git a/vga-core/vga_pll.v b/vga-core/vga_pll.v
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+// megafunction wizard: %ALTPLL%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: altpll 

+

+// ============================================================

+// File Name: VgaPll.v

+// Megafunction Name(s):

+// 			altpll

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version

+// ************************************************************

+

+

+//Copyright (C) 1991-2005 Altera Corporation

+//Your use of Altera Corporation's design tools, logic functions 

+//and other software and tools, and its AMPP partner logic       

+//functions, and any output files any of the foregoing           

+//(including device programming or simulation files), and any    

+//associated documentation or information are expressly subject  

+//to the terms and conditions of the Altera Program License      

+//Subscription Agreement, Altera MegaCore Function License       

+//Agreement, or other applicable license agreement, including,   

+//without limitation, that your use is for the sole purpose of   

+//programming logic devices manufactured by Altera and sold by   

+//Altera or its authorized distributors.  Please refer to the    

+//applicable agreement for further details.

+

+

+// synopsys translate_off

+`timescale 1 ps / 1 ps

+// synopsys translate_on

+module vga_pll (

+	clock_in,

+	clock_out);

+

+	input	  clock_in;

+	output	  clock_out;

+

+	wire [5:0] clock_output_bus;

+	wire [1:0] clock_input_bus;

+	wire gnd;

+	

+	assign gnd = 1'b0;

+	assign clock_input_bus = { gnd, clock_in }; 

+

+	altpll	altpll_component (

+				.inclk (clock_input_bus),

+				.clk (clock_output_bus)

+				);

+	defparam

+		altpll_component.operation_mode = "NORMAL",

+		altpll_component.intended_device_family = "Cyclone II",

+		altpll_component.lpm_type = "altpll",

+		altpll_component.pll_type = "FAST",

+		/* Specify the input clock to be a 50MHz clock. A 50 MHz clock is present

+		 * on PIN_N2 on the DE2 board. We need to specify the input clock frequency

+		 * in order to set up the PLL correctly. To do this we must put the input clock

+		 * period measured in picoseconds in the inclk0_input_frequency parameter.

+		 * 1/(20000 ps) = 0.5 * 10^(5) Hz = 50 * 10^(6) Hz = 50 MHz. */

+		altpll_component.inclk0_input_frequency = 20000,

+		altpll_component.primary_clock = "INCLK0",

+		/* Specify output clock parameters. The output clock should have a

+		 * frequency of 25 MHz, with 50% duty cycle. */

+		altpll_component.compensate_clock = "CLK0",

+		altpll_component.clk0_phase_shift = "0",

+		altpll_component.clk0_divide_by = 2,

+		altpll_component.clk0_multiply_by = 1,		

+		altpll_component.clk0_duty_cycle = 50;

+		

+	assign clock_out = clock_output_bus[0];

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"

+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"

+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"

+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"

+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"

+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"

+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"

+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"

+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"

+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"

+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"

+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"

+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"

+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"

+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"

+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"

+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"

+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"

+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"

+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"

+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"

+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"

+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"

+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"

+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"

+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"

+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"

+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"

+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"

+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"

+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"

+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"

+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"

+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"

+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"

+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"

+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"

+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"

+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"

+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"

+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"

+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"

+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"

+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"

+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"

+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"

+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"

+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"

+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"

+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"

+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"

+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"

+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"

+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"

+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"

+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000"

+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"

+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"

+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"

+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"

+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"

+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"

+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"

+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"

+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"

+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"

+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"

+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"

+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"

+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"

+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"

+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"

+// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"

+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"

+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"

+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"

+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"

+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"

+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"

+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"

+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0

+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0

+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.v TRUE FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.inc FALSE FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.cmp FALSE FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.bsf FALSE FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_inst.v FALSE FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_bb.v FALSE FALSE